[求助] 用FPGA做频率为50hz的电压采集

yuechenping 2014-4-16 11:46 楼主

用FPGA做频率为50hz的电压采集，刚开始能显示采集到电压值和采集的电压频率为50hz，上电一段时间（几个小时）后，电压值正常，但是频率采集不到了，变为了0，请问大侠们这是什么原因啊？急用！！！

回复评论（12）

沙发 chenzhufly

频率的处理算法是否有问题啊

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点赞 2014-4-16 12:51

4楼 chunyang

这个显然是设计问题，但具体是哪里的问题就无法从楼主的描述中获知了。

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点赞 2014-4-16 16:26

5楼 yuechenping

引用: chunyang 发表于 2014-4-16 16:26
这个显然是设计问题，但具体是哪里的问题就无法从楼主的描述中获知了。

硬件问题，还是软件啊？我的采集频率是10Mhz，下面是我的频率计算方法：
module freq(
input f_in,
input f_start,
// output reg f_end,
output reg [15:0] freq_datah16,
   output reg [7:0] freq_datal8,
   output reg  freq2_rate_state, //added 101015
input clk_f //100623: clock : 10Mhz
);

//-----------------freq_measure fsm------------------------------
reg [23:0] freqcount = 0;

parameter st0 = 0;
parameter st1 = 1;
parameter st2 = 2;
parameter st3 = 3;
parameter st4 = 4;
parameter st5 = 5;
parameter st6 = 6;
parameter st7 = 7;
parameter st8 = 8;

reg [3:0] state = st0;
//added 101019
reg [23:0] f_mea_cnt;

always@( posedge clk_f )
begin
      case (state)
         st0 : begin       //idle
      if(f_start)
state <= st1;
else
state <= st0;

               freqcount <= 0;
            freq_datah16 <= 0;
freq_datal8 <= 0;
freq2_rate_state <= 0;
               end
         st1 : begin
      if(!f_in)
state <= st2;
else if (f_mea_cnt >= 300000)
state <= st6;
else
state <= st1;

   freqcount <= 0;
   f_mea_cnt <= f_mea_cnt + 1;
               end
st2 : begin
   if( f_in )
               state <= st3;
else if (f_mea_cnt >= 300000)
state <= st6;
else
      state <= st2;

freqcount <= freqcount +1;
               f_mea_cnt <= f_mea_cnt + 1;

end
st3 : begin
               if(!f_in)
      state <= st4;
else if (f_mea_cnt >= 300000)
state <= st6;
else
state <= st3;

freqcount <= freqcount + 1;
               f_mea_cnt <= f_mea_cnt + 1;
end
st4 : begin
state <= st1;

if(freq2_rate_state == 1)
freq2_rate_state <= 0;
else
freq2_rate_state <= 1;

freq_datah16 <= freqcount[23:8];
freq_datal8 <= freqcount[7:0];
         f_mea_cnt <= 0;
end

   st5 : begin

               state <= st1;

freqcount <= 0;
               end
   st6 : begin

               state <= st1;

freqcount <= 0;
freq_datah16 <= 0;
freq_datal8 <= 0;
f_mea_cnt <= 0;
freq2_rate_state <= 1;
               end

   default: begin  // Fault Recovery
            state <= st0;

               freqcount <= 0;
            freq_datah16 <= 0;
   freq_datal8 <= 0;
      end
      endcase

end




endmodule

点赞 2014-4-17 09:15

6楼 yuechenping

引用: chenzhufly 发表于 2014-4-16 12:51
频率的处理算法是否有问题啊

频率算法是：
module freq(
input f_in,
input f_start,
// output reg f_end,
output reg [15:0] freq_datah16,
   output reg [7:0] freq_datal8,
   output reg  freq2_rate_state, //added 101015
input clk_f //100623: clock : 10Mhz
);

//-----------------freq_measure fsm------------------------------
reg [23:0] freqcount = 0;

parameter st0 = 0;
parameter st1 = 1;
parameter st2 = 2;
parameter st3 = 3;
parameter st4 = 4;
parameter st5 = 5;
parameter st6 = 6;
parameter st7 = 7;
parameter st8 = 8;

reg [3:0] state = st0;
//added 101019
reg [23:0] f_mea_cnt;

always@( posedge clk_f )
begin
      case (state)
         st0 : begin       //idle
      if(f_start)
state <= st1;
else
state <= st0;

               freqcount <= 0;
            freq_datah16 <= 0;
freq_datal8 <= 0;
freq2_rate_state <= 0;
               end
         st1 : begin
      if(!f_in)
state <= st2;
else if (f_mea_cnt >= 300000)
state <= st6;
else
state <= st1;

   freqcount <= 0;
   f_mea_cnt <= f_mea_cnt + 1;
               end
st2 : begin
   if( f_in )
               state <= st3;
else if (f_mea_cnt >= 300000)
state <= st6;
else
      state <= st2;

freqcount <= freqcount +1;
               f_mea_cnt <= f_mea_cnt + 1;

end
st3 : begin
               if(!f_in)
      state <= st4;
else if (f_mea_cnt >= 300000)
state <= st6;
else
state <= st3;

freqcount <= freqcount + 1;
               f_mea_cnt <= f_mea_cnt + 1;
end
st4 : begin
state <= st1;

if(freq2_rate_state == 1)
freq2_rate_state <= 0;
else
freq2_rate_state <= 1;

freq_datah16 <= freqcount[23:8];
freq_datal8 <= freqcount[7:0];
         f_mea_cnt <= 0;
end

   st5 : begin

               state <= st1;

freqcount <= 0;
               end
   st6 : begin

               state <= st1;

freqcount <= 0;
freq_datah16 <= 0;
freq_datal8 <= 0;
f_mea_cnt <= 0;
freq2_rate_state <= 1;
               end

   default: begin  // Fault Recovery
            state <= st0;

               freqcount <= 0;
            freq_datah16 <= 0;
   freq_datal8 <= 0;
      end
      endcase

end




endmodule

点赞 2014-4-17 09:15