[求助] 运用EPWM1-3输出六路三项晶闸管触发脉冲的问题

1500231580 2014-5-14 19:42 楼主

本人不知道如何设置PWM模块的值，跪求给出设置程序？以下是我完成的部分程序，请高手指点迷津

void InitEPwm1Example()
{

// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBPRD = 1500;                   // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;    // Disable phase loading
EPwm1Regs.TBPHS.half.TBPHS = 0;    // Phase is 0
EPwm1Regs.TBCTR = 0x0000;                // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set Compare values
EPwm1Regs.CMPA.half.CMPA =100; // Set compare A value
EPwm1Regs.CMPB = 200;             // Set Compare B value

// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;          // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CBU = AQ_CLEAR;       // Clear PWM1A on event A, up count

EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;          // Set PWM1B on Zero
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;       // Clear PWM1B on event B, up count

// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1;             // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;          // Generate INT on 3rd event

// Information this example uses to keep track
// of the direction the CMPA/CMPB values are
// moving, the min and max allowed values and
// a pointer to the correct ePWM registers
epwm1_info.EPwm_CMPA_Direction = 1;          // Start by increasing CMPA & CMPB
epwm1_info.EPwm_CMPB_Direction = 1;
epwm1_info.EPwmTimerIntCount = 0;          // Zero the interrupt counter
epwm1_info.EPwmRegHandle = &EPwm1Regs;       // Set the pointer to the ePWM module

}

void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBPRD = 1500;                   // Set timer period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBPHS.half.TBPHS = 0x0000;    // Phase is 0
EPwm2Regs.TBCTR = 1400;                // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

// Setup shadow register load on ZERO
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set Compare values
EPwm2Regs.CMPA.half.CMPA = 500;          // Set compare A value
EPwm2Regs.CMPB = 600;                   // Set Compare B value

// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;          // Clear PWM2A on Period
EPwm2Regs.AQCTLA.bit.CBU =AQ_CLEAR;             // Set PWM2A on event A, up count

EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;          // Clear PWM2B on Period
EPwm2Regs.AQCTLB.bit.CAD =AQ_CLEAR;             // Set PWM2B on event B, up count

// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;       // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1;                // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;             // Generate INT on 3rd event

// Information this example uses to keep track
// of the direction the CMPA/CMPB values are
// moving, the min and max allowed values and
// a pointer to the correct ePWM registers
epwm2_info.EPwm_CMPA_Direction = 1;             // Start by increasing CMPA
epwm2_info.EPwm_CMPB_Direction = 1;             // and decreasing CMPB
epwm2_info.EPwmTimerIntCount = 0;             // Zero the interrupt counter
epwm2_info.EPwmRegHandle = &EPwm2Regs;          // Set the pointer to the ePWM module

}

void InitEPwm3Example(void)
{

// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBPRD = 1000;                   // Set timer period
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBPHS.half.TBPHS = 0;    // Phase is 0
EPwm3Regs.TBCTR = 1300;                // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV2;

// Setup shadow register load on ZERO
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

  // Set Compare values
EPwm3Regs.CMPA.half.CMPA = 1000;          // Set compare A value
EPwm3Regs.CMPB = 1100;                   // Set Compare B value

// Set Actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;       // Set PWM3A on event B, up count
EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR;    // Clear PWM3A on event B, up count

EPwm3Regs.AQCTLB.bit.CBD = AQ_TOGGLE;    // Toggle EPWM3B on Zero
EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
// Interrupt where we will change the Compare Values
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1;             // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;          // Generate INT on 3rd event

// Start by increasing the compare A and decreasing compare B
epwm3_info.EPwm_CMPA_Direction = 1;
epwm3_info.EPwm_CMPB_Direction = 1;
// Start the cout at 0
epwm3_info.EPwmTimerIntCount = 0;
epwm3_info.EPwmRegHandle = &EPwm3Regs;

}