[讨论] altera 4s系列编译出错

4s系列编译出了错误，
Error: Following nodes require the same Clock Control Block CLKCTRL_R8
        Error: Node "pll1:inst1|altpll:altpll_component|pll1_altpll:auto_generated|wire_pll1_clk[4]" is currently placed at location counter C1 of PLL_L3 with a Global Signal type of Dual-Regional Clock
        Error: Node "plla:inst|altpll:altpll_component|plla_altpll:auto_generated|wire_pll1_clk[5]" is currently placed at location counter C0 of PLL_L2 with a Global Signal type of Regional Clock

求大神知道的给个解释呗！