[讨论] 【紧急求助】 xilinx cordic ip 核 仿真时遇到的问题

我用cordic 核实现开方功能，但是用modelsim  仿真的时候输出一直是蓝线，提示很多很多warning # Loading work.sqare_test_tb # Loading work.square_test # Loading work.square # Loading D:\X\ISE\verilog\mti_se\XilinxCoreLib_ver.C_REG_FD_V7_0 # Loading D:\X\ISE\verilog\mti_se\XilinxCoreLib_ver.C_SHIFT_RAM_V7_0 # Loading D:\X\ISE\verilog\mti_se\XilinxCoreLib_ver.C_ADDSUB_V7_0 # Loading D:\X\ISE\verilog\mti_se\XilinxCoreLib_ver.C_MUX_BIT_V7_0 # Loading D:\X\ISE\verilog\mti_se\unisims_ver.LUT4 # Loading D:\X\ISE\verilog\mti_se\unisims_ver.BUF # Loading work.glbl # ** Warning: (vsim-3017) square.v(872): [TFMPC] - Too few port connections. Expected 10, found 4. #         Region: /sqare_test_tb/uut/YourInstanceName/BU20 # ** Warning: (vsim-3722) square.v(872): [TFMPC] - Missing connection for port 'SINIT'. # ** Warning: (vsim-3722) square.v(872): [TFMPC] - Missing connection for port 'SSET'. # ** Warning: (vsim-3722) square.v(872): [TFMPC] - Missing connection for port 'SCLR'. # ** Warning: (vsim-3722) square.v(872): [TFMPC] - Missing connection for port 'AINIT'. # ** Warning: (vsim-3722) square.v(872): [TFMPC] - Missing connection for port 'ASET'. # ** Warning: (vsim-3722) square.v(872): [TFMPC] - Missing connection for port 'CE'. # ** Warning: (vsim-3017) square.v(902): [TFMPC] - Too few port connections. Expected 10, found 4. #         Region: /sqare_test_tb/uut/YourInstanceName/BU89 # ** Warning: (vsim-3722) square.v(902): [TFMPC] - Missing connection for port 'SINIT'. # ** Warning: (vsim-3722) square.v(902): [TFMPC] - Missing connection for port 'SSET'. # ** Warning: (vsim-3722) square.v(902): [TFMPC] - Missing connection for port 'SCLR'. # ** Warning: (vsim-3722) square.v(902): [TFMPC] - Missing connection for port 'AINIT'. # ** Warning: (vsim-3722) square.v(902): [TFMPC] - Missing connection for port 'ASET'. # ** Warning: (vsim-3722) square.v(902): [TFMPC] - Missing connection for port 'CE'. # ** Warning: (vsim-3017) square.v(932): [TFMPC] - Too few port connections. Expected 10, found 4. ..... 另请教高手们，我现在要实现的算法，好像不大容易避免开方，有没有别的办法实现开方 或者 对一个复数求模值呢

warning

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cordic 核的设置1

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cordic 核的设置2

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cordic 核的设置3

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cordic 核的设置4

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modeisim 仿真

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COrdic求开方已经是最方便的算法了，没有其他更好的办法。 你把你代码贴上去我可以帮你看看。

哦，谢谢，即使单独将Cordic的ip核拿出来做仿真，这样设置后，结果也是高祖态。不知道什么原因？？仿真代码：module Cor_tb;

        // Inputs
        reg [31:0] x_in;
        reg clk;
        reg ce;
        reg sclr;

        // Outputs
        wire [16:0] x_out;

        // Instantiate the Unit Under Test (UUT)
        Cordic uut (
                .x_in(x_in),
                .clk(clk),
                .ce(ce),
                .sclr(sclr),
                .x_out(x_out)
        );

        initial begin
                // Initialize Inputs
                x_in = 0;
                clk = 0;
                ce = 0;
                sclr = 0;

                // Wait 100 ns for global reset to finish
                #40;
                ce=0;
                end
               
                always #10 clk=~clk;
                always @(posedge clk)
                x_in<=x_in+100;
               
        
                // Add stimulus here
      
endmodule

很简单的CORDIC核的调用，但是仿真时就是不通过。。不知道什么原因，是设置问题，还是测试代码的问题，我检查不出来。麻烦大神帮忙看下。。