[经验] High Performance, FPGA-Optimized LDPC for Storage

白丁 2015-12-6 15:25 楼主

LDPC and Error Correcting Codes

BCH codes are running out of steam

• Can’t take advantage of soft-data
• Performance is limited to the Shannon limit for a hard channel

LDPC codes

• Near Shannon-limit performance
• Take advantage of soft-data
• Good implementations of LDPC codes are low power and cost effective

No standards for LDPC in storage space

Code “growth” technology with best-in-class coding performance

at very low cost

Sub-system block diagram
DSP work is focused on the LDPC encoder, decoder and statistics processing below

Xilinx LDPC Features

Best-in-class code performance near Shannon limit
Achieved low error floor under 10-15 with proprietary optimization method
Support for code rate change on-the-fly
Support both hard decision and soft decision decoding
High throughput and low latency performance
Scalable architecture supporting various options
FPGA optimized for minimal area/power
Provides decoder status and statistics interfaces

Xilinx LDPC Specifications

Raw BER v.s. Frame Error Rate

Advanced code construction methodology for best code performance
Achieved low error floor using proprietary optimization technique
Near Shannon limit performance

LDPC v.s. BCH Performance

Error Floor Free Performance

Error Correction Capability

LDPC Implementation

Single LDPC instance for easy integration
Achieve 400 MHz on 7 series and UltraScale™ FPGAs
Small footprint – low LUT counts

Hardware Reference Board

Summary

Xilinx offers LDPC with industry-leading
performance in all aspects:
• Error floor
• Resource utilization
• BER performance
• Throughput

training