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| module dge( input wire sclk, input wire rst_n, input wire a, output wire led ); reg a_reg; reg podge;//posedge reg nedge;//negedge /* 通过寄存器打一拍得到的a_reg是 信号a的前一个时钟周期的值 */ always@(posedge sclk or negedge rst_n) if(!rst_n) a_reg <= 1'b0; else a_reg <= a; /* 上升沿的出现取决于信号a的现态为1， 现态的前一个状态为0 */ always@(posedge sclk or negedge rst_n) if(!rst_n) podge <= 1'b0; else if((a == 1'b1) && (a_reg == 1'b0)) //({a,a_reg} == 2'b10) podge <= 1'b1; else podge <= 1'b0; /* 下降沿的出现取决于信号a的现态为0， 现态的前一个状态为1 */ always@(posedge sclk or negedge rst_n) if(!rst_n) nedge <= 1'b0; else if((a == 1'b0) && (a_reg == 1'b1)) //({a,a_reg} == 2'b01) nedge <= 1'b1; else nedge <= 1'b0; assign led = nedge && podge; endmodule |
| `timescale 1ns/1ns module tb_dge(); reg sclk; reg rst_n; reg a; wire led; dge dge_inst( .sclk (sclk), .rst_n (rst_n), .a (a), .led (led) ); initial sclk = 1; always #10 sclk = ~sclk; initial begin rst_n <= 0; a <= 0; #40; rst_n <= 1; #120; a <= 1; #40; a <= 0; #80; a <= 1; #60; a <= 0; end endmodule |
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引用: reallmy 发表于 2016-10-24 18:32
打拍那个补充一下，a信号必须是输入clk时钟域的信号，如果a与clk不是一个时钟域的则需要再打三拍，用后两拍 ...
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