[求助] Illegal grid period. Grid period must be greater than 0.

测试的代码：
[mw_shl_code=c,false]`timescale 1ps /1ps

module clk_tst;

reg clk = 0;
initial
#20

repeat(30)
begin
#20
        clk = ~clk;
end
endmodule[/code]

开始仿真就会出现如下错误：
Illegal grid period. Grid period must be greater than 0.
大家以前遇到过这个问题吗，该怎么解决，谢谢！