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-- Company:
-- Engineer:
--
-- Create Date: 2016/09/28 15:27:13
-- Design Name:
-- Module Name: hv_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hv_ctrl is
Port (
sys_clk : in std_logic;
reset : in std_logic;
make_data : in std_logic;
MData_Off : in std_logic; -- use to stop x-ray from DMS, active high.
hv_reset_com : in std_logic;-----------------------------------
contactor_on_com : in std_logic;-----------------------------------
Starter_com_pulse : in std_logic;-----------------------------------
starter_on_com : in std_logic;-----------------------------------
x_prep_com : in std_logic;-----------------------------------
hv_on_com : in std_logic;-----------------------------------
fi_off_com : in std_logic;-----------------------------------
Fi_standby_mode : in std_logic;---------cmd from slipring---------
starter_off_mode : in std_logic;-----------------------------------
kv_ref_pulse : in std_logic;-----------------------------------
hv_on_pulse : in std_logic;-----------------------------------
fila_com_pulse : in std_logic;-----------------------------------
fila_host_data : in std_logic_vector(11 downto 0);--------------
ETime_ref_pulse : in std_logic;----------------------------------- expo time setting pulse
expo_time_ref : in std_logic_vector(15 downto 0);-------------- expo time
hss_h_speed_com : in std_logic;----------------------------------- 0:high/1:low
hss_speed_pulse : in std_logic;-----------------------------------
fil_fs_choice : in std_logic;-----------------------------------
NLTest_com : in std_logic;-----------------------------------
hss_h_speed_out : out std_logic;----------------------------------- to HVG HW, 0:high/1:low
opto_intensity : in std_logic;
-- RX_READY_in : in std_logic;
opto_intensity_out: out std_logic;
contactor_on_flag : out std_logic;---------------------------------- contactor on feedback from HVG
contactor_status : in std_logic;-----------------------------------
starter_status : in std_logic;----------------------------------- active high
hv_on_status : in std_logic;-----------------------------------
hv_fault : in std_logic;---status from HVG HW interface----
hv_jb1_status : in std_logic;-----------------------------------
hv_jb2_status : in std_logic;-----------------------------------
hv_err_data : in std_logic_vector(7 downto 0);--------------- DFD
HVcrc_ack : in std_logic;----------------------------------- this one is active low
fila_fd_data : in std_logic_vector(12 downto 0);--------------
HV_fil_sel_stat : in std_logic;-----------------------------------
hv_hss_h_speed_stat: in std_logic;----------------------------------- 0 low/1 high
hverr_reg_choice : out std_logic_vector(2 downto 0);-------------- DFA
hv_starter_on : out std_logic;----------------------------------
hv_ret_out : out std_logic;-----cmd to HVG HW interface------ reset
hv_on_out : out std_logic;----------------------------------
fi_off_out : out std_logic;----------------------------------
Host_Abort_CMD : in std_logic;
tube_temp1 : in std_logic; --Tube_TS ,high is normal(switch close)
tube_flowswitch : in std_logic; --Tube_FS ,high is normal(switch close)
Gsend_fault : in std_logic;
KVsend_fault : in std_logic;
door_open_status : in std_logic;--from RCB_Module slipring, 1 door open/0 door close
HV_fault_out : out std_logic;
door_status : out std_logic;
pre_scan_flag : in std_logic;
E_stop_mode : out std_logic_vector(2 downto 0);
exp_time_fd : out std_logic_vector(15 downto 0); -- exposure time fdbk
HV_ready : out std_logic;-------- status to rcb_top -------------
hv_on_status_syn : out std_logic;----------------------------------------
hv_fault_syn : out std_logic;----------------------------------------
hv_state4_byte3 : out std_logic_vector(7 downto 0); -- fdbk
hv_state4_byte2 : out std_logic_vector(7 downto 0); -- fdbk
hv_state4_byte1 : out std_logic_vector(7 downto 0); -- fdbk
hv_state4_byte0 : out std_logic_vector(7 downto 0); -- fdbk
hv_state3_byte3 : out std_logic_vector(7 downto 0); -- fdbk
hv_state3_byte2 : out std_logic_vector(7 downto 0); -- fdbk
hv_state3_byte1 : out std_logic_vector(7 downto 0); -- fdbk
hv_state3_byte0 : out std_logic_vector(7 downto 0); -- fdbk
hv_state232_byte1 : out std_logic_vector(7 downto 0); -- rs232 fdbk
hv_state232_byte0 : out std_logic_vector(7 downto 0); -- rs232 cmd
hv_falut1 : out std_logic_vector(7 downto 0); -- rs232 fault fdbk from HVG1
hv_falut2 : out std_logic_vector(7 downto 0); -- rs232 fault fdbk from HVG2
fi_pro_pulse : out std_logic; -- filament protect EN
clk_1ms_pulse : out std_logic;
TP : out STD_LOGIC_VECTOR (23 downto 0)
);
end hv_ctrl;
architecture Behavioral of hv_ctrl is
constant RESET_ACTIVE : std_logic := '0';
constant Boost_time : std_logic_vector(7 downto 0) :="11010010"; --21 Seconds
constant Brake_time : std_logic_VECTOR(7 downto 0) :="10010110"; --15 Seconds
constant Shut_time : std_logic_VECTOR(11 downto 0) :="001011101110"; --75 Seconds
--constant standby_ref : std_logic_vector(11 downto 0) := "100000000000";--3.0A
signal contactor_status_in : std_logic;
signal starter_status_in : std_logic;
signal starter_status_input,starter_status_input1,starter_delay1ms,starter_delay2ms: std_logic;
signal hv_on_status_in : std_logic;
signal hv_fault_in : std_logic;
signal hv_jb1_status_in : std_logic;
signal hv_jb2_status_in : std_logic;
signal tube_temp1_in : std_logic;
signal tube_flowswitch_in : std_logic;
signal READY : std_logic_VECTOR(14 downto 0);
--signal READY : std_logic_VECTOR(11 downto 0);
signal hv_reg_reset : std_logic;
signal exposure_limit_time : std_logic;
--signal exposure_time : std_logic;
signal HV_preset_timer : std_logic_vector(15 downto 0);
signal exp_time_feed : std_logic_vector(15 downto 0);
signal starter_status_fd : std_logic_vector(1 downto 0);
signal hvwork_mode_fd : std_logic_vector(1 downto 0);
signal hverr_data_in : std_logic_vector(7 downto 0);
signal HVcrc_ack_in : std_logic;
signal count_100s : std_logic_vector(9 downto 0);
signal count_100ms : std_logic_vector(9 downto 0);
signal delay20ms : std_logic_vector(4 downto 0);
signal clk1ms_timer : std_logic_VECTOR(15 downto 0);
signal clk1ms_pulse : std_logic;
signal clk10ms_timer : std_logic_VECTOR(3 downto 0);
signal clk10ms_pulse : std_logic;
signal clk100ms_timer : std_logic_VECTOR(6 downto 0);
signal clk100ms_pulse : std_logic;
signal count_3ms : std_logic_vector(2 downto 0);
signal Rwave_timer : std_logic_VECTOR(9 downto 0);
signal door_status_in : std_logic;
signal mareg_e : std_logic;
signal kvreg_e : std_logic;
signal starter_e,starter_e_del1,starter_e_del2,starter_e_del3: std_logic;
signal inv_tmp : std_logic;
signal uncommanded_exp : std_logic;
signal nltest_status : std_logic;
signal vma_status : std_logic;
signal hv_test_mode : std_logic;
signal h_speed_warning : std_logic;
signal hss_h_speed_sig : std_logic;
signal starter_off_flag : std_logic;
signal starter_self_off : std_logic;
signal starter_off_cnt : std_logic_vector(11 downto 0);
type ShutStatus is (idle,shut_time_on);
signal shut_state : ShutStatus;
signal a_ov : std_logic;
signal c_ov : std_logic;
signal a_oi : std_logic;
signal c_oi : std_logic;
signal fi_oi : std_logic;
signal arc : std_logic;
signal gm_on_status : std_logic;
signal tube_return_err : std_logic;
signal starter_dc_rail : std_logic;
signal starter_i_fed : std_logic;
signal ipm_dec : std_logic;
signal grid_inf_status : std_logic;
signal grid_ref_e : std_logic;
signal grid_stb_e : std_logic;
signal grid_frq_e : std_logic;
signal xray_ot_e : std_logic;
signal invert_error : std_logic;
signal precharge_fail : std_logic;
signal invert_over_c : std_logic;
signal c_high_arc : std_logic;
signal FIL_SC : std_logic;
signal a_high_arc : std_logic;
signal GM_SC : std_logic;
signal scb_fm_ver : std_logic_vector(7 downto 0);
signal scb_hw_ver : std_logic_vector(2 downto 0);
signal hv_type : std_logic_vector(2 downto 0);
signal hss_fm_ver : std_logic_vector(9 downto 0);
signal max_exp_timer:std_logic_VECTOR(13 downto 0);
signal max_exp_over:std_logic; --100 seconds
signal HVon_load_over:std_logic;
signal timer_over:std_logic_VECTOR(1 downto 0);
signal make_data_d1,make_data_d2:std_logic;
signal mdata_off_d1,mdata_off_d2:std_logic;
signal hv_on_out_status,hv_on_out_status_d1,hv_on_out_status_d2:std_logic;
signal generate_ret:std_logic;
signal READY_logic,READY_logic_delay,READY_logic_delay1ms,READY_logic_delay2ms,READY_logic_delay3ms:std_logic;
signal HV_fault_temp,HV_fault_delay1ms,HV_fault_delay2ms,HV_fault_delay3ms,HV_fault_delay4ms:std_logic;
signal HV_fault_status:std_logic;
signal HV_status_manual,HV_status_manual_del0ms,HV_status_manual_del1ms,HV_status_manual_del2ms:std_logic;
signal hv_hss_h_speed_com1,hv_hss_h_speed_com2,hv_hss_h_speed_com3:std_logic;
signal starter_on : std_logic;
signal boosting : std_logic;
signal braking : std_logic;
signal brake_flag : std_logic;
signal counter_20_40min : std_logic_vector(15 downto 0);
signal counter : std_logic_vector(7 downto 0);
signal opto_intensity_in : std_logic;
--signal RX_READY_in_syn : std_logic;
signal fila_error_count : std_logic_vector(6 downto 0);
signal fila_error_flag : std_logic;
signal byte8_temp : std_logic_vector(4 downto 0);
signal fsm_cnt : std_logic_vector(7 downto 0);
signal hv_fault_syn_temp : std_logic;
type StatorProtection is (idle,wait_high_ready,wait_low_ready,wait_brake_ready,boost_status,brake_status);
signal prt_status_stator : StatorProtection;
type Filastatus is (idle,count_100ms_status,protect,protect1);
signal prt_status : Filastatus;
type HVregstatus is (idle_initial,read_hv_version0,version1_addr,read_hv_version1,version2_addr,read_hv_version2,
idle,read_reg0,out_addr1,read_reg1,out_addr2,read_reg2,out_addr3,read_reg3,out_addr4,read_reg4);
signal prt_status_hv : HVregstatus;
type HVReady is (idle,latch_err,clear_err);
signal prt_status_door: HVReady;
signal make_data_delay1ms,make_data_delay2ms :std_logic;
signal mdata_off_delay1ms,mdata_off_delay2ms :std_logic;
signal small_arc_count : std_logic_vector(7 downto 0);
signal sarc_100ms_count: std_logic_vector(7 downto 0);
type SArc_status is (idle,send_arc_count,delay_100ms);
signal prt_status_SArc: SArc_status;
signal clk5ms_timer : std_logic_VECTOR(3 downto 0);
signal clk5ms_pulse : std_logic;
signal fi_off_logic : std_logic;
--attribute mark_debug: string;
--attribute mark_debug of hv_on_out_status : signal is "true";
--attribute mark_debug of hv_fault_syn_temp : signal is "true";
--attribute mark_debug of hv_on_status_in : signal is "true";
--attribute mark_debug of HV_status_manual : signal is "true";
--attribute mark_debug of nltest_status : signal is "true";
--attribute mark_debug of hverr_reg_choice : signal is "true";
--attribute mark_debug of fsm_cnt : signal is "true";
--attribute mark_debug of hss_h_speed_sig : signal is "true";
begin
TP(14 downto 0) <= READY;
TP(15) <= hv_on_out_status;
TP(16) <= hv_on_status_in;
TP(17) <= mdata_off_d2;
TP(23 downto 18) <= "000000";
hss_h_speed_out <= hss_h_speed_sig;
fi_off_out <= fi_off_logic;
door_status <= door_status_in;
hv_on_status_syn <= hv_on_status_in;
HV_ready<=READY_logic_delay;
hv_on_out<=hv_on_out_status;
hv_starter_on<=starter_on;
contactor_on_flag<=contactor_status_in;
HV_status_manual<=door_open_status and HV_status_manual_del1ms and HV_status_manual_del2ms;
HV_fault_temp<=arc or a_ov or c_ov or a_oi or c_oi or fi_oi or inv_tmp or starter_e_del3 or kvreg_e or mareg_e
or uncommanded_exp or KVsend_fault or byte8_temp(0) or byte8_temp(1) -- uncomamanded expo/crc err/ref_oc/ref_ov
or byte8_temp(4) or tube_return_err or (not hv_jb1_status_in) or (not hv_jb2_status_in) or hv_fault_in -- FI_fault/FCRW_status/DFA
or (not tube_temp1_in)or (not tube_flowswitch_in) or max_exp_over or fila_error_flag; -- filament over current
HV_fault_status<=HV_fault_temp and HV_fault_delay1ms and HV_fault_delay2ms and HV_fault_delay3ms and HV_fault_delay4ms;
READY<=x_prep_com & fi_off_logic & contactor_status_in & starter_status_in & hv_fault_in & hv_jb1_status_in &
hv_jb2_status_in & tube_temp1_in & '1' & tube_flowswitch_in & hv_reg_reset & reset & door_open_status & starter_status_fd;
-- hv_jb2_status_in & tube_temp1_in & '1' & tube_flowswitch_in & hv_reg_reset & reset & door_open_status & "11";
-- READY <= "111101111101011";
READY_logic_delay<=READY_logic or READY_logic_delay1ms or READY_logic_delay2ms or READY_logic_delay3ms;
starter_status_input<=starter_status_in and starter_delay1ms and starter_delay2ms;
starter_status_input1<=starter_status_in or starter_delay1ms or starter_delay2ms; -- fdbk: starter off
starter_e_del3<=starter_e_del2 and starter_e_del1 and starter_e;
timer_over<=max_exp_over & HVon_load_over;
exp_time_fd<=exp_time_feed;
clk_1ms_pulse<=clk1ms_pulse;
opto_intensity_out<=opto_intensity_in;
---------rs232-------------
hv_state232_byte0<= fi_off_logic &hv_on_out_status&x_prep_com&hv_reset_com& NLTest_com & (not fil_fs_choice) &starter_on& contactor_on_com; --rs232 cmd
hv_state232_byte1<=hv_fault_in & (not hss_h_speed_sig) &hv_hss_h_speed_stat &contactor_status_in &hv_on_status_in &HV_fil_sel_stat &starter_status_fd; --rs232 fdbk
hv_falut1 <= mareg_e & kvreg_e & starter_e_del3 & inv_tmp & uncommanded_exp & tube_return_err & byte8_temp(4) & nltest_status;-- rs232 fault fdbk from HVG1
hv_falut2 <= a_ov & c_ov & a_oi & c_oi & fi_oi & arc & byte8_temp(0) & byte8_temp(1);-- rs232 fault fdbk from HVG2
---------status frame------------
hv_state4_byte3<= "000000" & (not tube_temp1_in) & (not tube_flowswitch_in);
hv_state4_byte2<= fila_error_flag & h_speed_warning & byte8_temp(4) & byte8_temp(1) & byte8_temp(0) & tube_return_err & arc & hv_fault_syn_temp;
hv_state4_byte1<= fi_oi & uncommanded_exp & c_oi & door_status_in & a_oi & KVsend_fault & c_ov & a_ov;
hv_state4_byte0<= inv_tmp & starter_e_del3 & kvreg_e & (not hv_jb2_status_in) & (not hv_jb1_status_in) & hv_fault_in & mareg_e & max_exp_over;
hv_state3_byte3<='0'&'0'&'0'&'0'&'0'&'0'&'0'&hv_on_status_in; -- 0x03,byte3
hv_state3_byte2<=hv_hss_h_speed_stat & HV_status_manual & '0'& tube_flowswitch_in & tube_temp1_in & hv_test_mode & nltest_status & Fi_standby_mode; -- 0x03,byte2
hv_state3_byte1<='0'&'0'& starter_off_flag & contactor_status_in & starter_status_input & HV_fil_sel_stat & starter_status_fd; -- 0x03,byte1
hv_state3_byte0<= fi_off_logic & hv_on_out_status & x_prep_com & (not hss_h_speed_sig) & NLTest_com & (not fil_fs_choice) & starter_on & contactor_on_com; -- 0x03,byte0
----------sync-------------
process(sys_clk)
begin
if sys_clk'event and sys_clk='1' then
contactor_status_in <=contactor_status;
starter_status_in <=starter_status;
hv_on_status_in <=hv_on_status;
hv_fault_in <=hv_fault;
hv_jb1_status_in <=hv_jb1_status;
hv_jb2_status_in <=hv_jb2_status;
tube_temp1_in <=tube_temp1;
tube_flowswitch_in <=tube_flowswitch;
hverr_data_in <=hv_err_data;
opto_intensity_in <=opto_intensity;
make_data_d1 <=make_data_delay2ms;
make_data_d2 <=make_data_d1;
mdata_off_d1 <=MData_Off; -- modify bug:last view end,HV is still on 20170411
mdata_off_d2 <=mdata_off_d1;
HVcrc_ack_in <=HVcrc_ack;
end if;
end process;
------------------------------------------------------
---------------Read FD0--FD7 register-----------------
------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
count_3ms<="000";
mareg_e <='0';
kvreg_e <='0';
starter_e <='0';
inv_tmp <='0';
uncommanded_exp <='0';
nltest_status <='0';
vma_status <='0';
hv_test_mode <='0';
a_ov <='0';
c_ov <='0';
a_oi <='0';
c_oi <='0';
fi_oi <='0';
arc <='0';
gm_on_status <='0';
tube_return_err <='0';
byte8_temp<=(others => '0');
starter_dc_rail <='0';
starter_i_fed <='0';
ipm_dec <='0';
grid_inf_status <='0';
grid_ref_e <='0';
grid_stb_e <='0';
grid_frq_e <='0';
xray_ot_e <='0';
invert_error <='0';
precharge_fail <='0';
invert_over_c <='0';
c_high_arc <='0';
FIL_SC <='0';
a_high_arc <='0';
GM_SC <='0';
scb_fm_ver <= (others => '0');
scb_hw_ver <= (others => '0');
hss_fm_ver <= (others => '0');
hv_type <= (others => '0');
hverr_reg_choice <= (others => '0');
prt_status_hv <= idle_initial;
elsif sys_clk'event and sys_clk ='1' then
case prt_status_hv is
when idle_initial =>
if clk1ms_pulse='1' then
prt_status_hv <= read_hv_version0;
hverr_reg_choice <= "111";
else
prt_status_hv <= idle_initial;
end if;
when read_hv_version0 =>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms <= (others => '0');
hss_fm_ver(7 downto 0) <= hverr_data_in;
prt_status_hv <= version1_addr;
else
count_3ms <= count_3ms + '1';
prt_status_hv <= read_hv_version0;
end if;
end if;
when version1_addr =>
hverr_reg_choice<="000";
prt_status_hv<=read_hv_version1;
when read_hv_version1 =>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms <= (others => '0');
hss_fm_ver(9 downto 8) <= hverr_data_in(7 downto 6);
scb_hw_ver <= hverr_data_in(5 downto 3);
hv_type <= hverr_data_in(2 downto 0);
prt_status_hv <= version2_addr;
else
count_3ms <= count_3ms + '1';
prt_status_hv <= read_hv_version1;
end if;
end if;
when version2_addr =>
hverr_reg_choice<="011";
prt_status_hv <= read_hv_version2;
when read_hv_version2 =>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms<=(others => '0');
scb_fm_ver <= hverr_data_in;
prt_status_hv <= idle;
else
count_3ms <= count_3ms + '1';
prt_status_hv <= read_hv_version2;
end if;
end if;
when idle=>
hverr_reg_choice<="001";
count_3ms<="000";
prt_status_hv<=read_reg0;
when read_reg0=>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms<=(others => '0');
mareg_e <=hverr_data_in(0);
kvreg_e <=hverr_data_in(1);
starter_e <=hverr_data_in(2);
inv_tmp <=hverr_data_in(3);
uncommanded_exp <=hverr_data_in(4);
nltest_status <= not hverr_data_in(5);
vma_status <=hverr_data_in(6); -- reserved
hv_test_mode <=hverr_data_in(7);
prt_status_hv<=out_addr1;
else
count_3ms<=count_3ms + '1';
prt_status_hv<=read_reg0;
end if;
end if;
when out_addr1=>
hverr_reg_choice<="010";
count_3ms<="000";
prt_status_hv<=read_reg1;
when read_reg1=>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms<=(others => '0');
a_ov <=hverr_data_in(0);
c_ov <=hverr_data_in(1);
a_oi <=hverr_data_in(2);
c_oi <=hverr_data_in(3);
fi_oi <=hverr_data_in(4);
arc <=hverr_data_in(5);
gm_on_status <=hverr_data_in(6); --reserved
tube_return_err <=hverr_data_in(7);
prt_status_hv<=out_addr2;
else
count_3ms<=count_3ms + '1';
prt_status_hv<=read_reg1;
end if;
end if;
when out_addr2=>
hverr_reg_choice<="100";
count_3ms<="000";
prt_status_hv<=read_reg2;
when read_reg2=>
if clk1ms_pulse='1' then
if count_3ms="010" then
byte8_temp(0)<=hverr_data_in(3); -- ref_oc, mA over programming
byte8_temp(1)<=hverr_data_in(4); -- ref_ov, kV over programming
byte8_temp(2)<=hverr_data_in(5); -- reserved
byte8_temp(3)<=hverr_data_in(6); -- reserved
byte8_temp(4)<=hverr_data_in(7); -- FI_fault, filament loop failure
count_3ms<=(others => '0');
prt_status_hv<=out_addr3;
else
count_3ms<=count_3ms + '1';
prt_status_hv<=read_reg2;
end if;
end if;
when out_addr3=>
hverr_reg_choice<="101";
prt_status_hv<=read_reg3;
when read_reg3=>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms<=(others => '0');
a_high_arc <= hverr_data_in(0);
GM_SC <= hverr_data_in(1);
c_high_arc <= hverr_data_in(2);
FIL_SC <= hverr_data_in(3);
invert_over_c <= hverr_data_in(4);
precharge_fail <= hverr_data_in(5);
invert_error <= hverr_data_in(6);
xray_ot_e <= hverr_data_in(7);
prt_status_hv<= out_addr4;
else
count_3ms<=count_3ms + '1';
prt_status_hv<= read_reg3;
end if;
end if;
when out_addr4=>
hverr_reg_choice<="110";
prt_status_hv<=read_reg4;
when read_reg4=>
if clk1ms_pulse='1' then
if count_3ms="010" then
count_3ms<=(others => '0');
grid_frq_e <=hverr_data_in(0);
grid_stb_e <=hverr_data_in(1);
grid_ref_e <=hverr_data_in(2);
grid_inf_status<=hverr_data_in(3);
ipm_dec <=hverr_data_in(4);
starter_i_fed <=hverr_data_in(5);
starter_dc_rail <=hverr_data_in(6);
prt_status_hv<=idle_initial;
else
count_3ms<=count_3ms + '1';
prt_status_hv<=read_reg4;
end if;
end if;
when others =>
count_3ms<=(others => '0');
prt_status_hv<=idle;
end case;
end if;
end process;
------------------------------------------------------
---------------Starter status feedback----------------
------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
starter_status_fd<="00";
elsif sys_clk'event and sys_clk ='1' then
if braking = '1' then
starter_status_fd<="01";
elsif boosting = '1' then
starter_status_fd<="10";
elsif starter_status_input ='1' then -- starter on fdbk
starter_status_fd<="11";
else
starter_status_fd<="00";
end if;
end if;
end process;
------------------------------------------------------
---------detect HV shut time whether enough-----------
------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
starter_off_flag <= '0';
starter_off_cnt <=(others => '0');
shut_state <= idle;
elsif sys_clk'event and sys_clk ='1' then
case shut_state is
when idle =>
if (Starter_com_pulse='1' and starter_on_com ='0' and starter_on ='1') or starter_self_off = '1' then -- console cmd: starter off
starter_off_flag <= '1';
-- starter_off_cnt <=starter_off_cnt + '1';
shut_state <= shut_time_on;
else
starter_off_cnt <=(others => '0');
starter_off_flag <= '0';
shut_state <= idle;
end if;
when shut_time_on =>
if clk100ms_pulse ='1' then
if starter_off_cnt = Shut_time then -- 75 secs
starter_off_flag <= '0';
starter_off_cnt <=(others => '0');
shut_state <= idle;
else
starter_off_flag <= '1';
starter_off_cnt <=starter_off_cnt + '1';
shut_state <= shut_time_on;
end if;
else
starter_off_flag <= starter_off_flag;
starter_off_cnt <= starter_off_cnt;
shut_state <= shut_time_on;
end if;
when others =>
starter_off_flag <= '0';
starter_off_cnt <=(others => '0');
shut_state <= idle;
end case;
end if;
end process;
-------------------------------------------------------
-----------HV work mode status feedback----------------
-------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
hvwork_mode_fd<="00";
elsif sys_clk'event and sys_clk ='1' then
if nltest_status = '1' then
hvwork_mode_fd<="01";
elsif vma_status = '1' then
hvwork_mode_fd<="10";
elsif hv_test_mode ='1' then
hvwork_mode_fd<="11";
else
hvwork_mode_fd<="00";
end if;
end if;
end process;
------------------------------------------------
-------detect hv_on_out rise/fall edge----------
------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
hv_on_out_status_d1<='0';
hv_on_out_status_d2<='0';
elsif sys_clk'event and sys_clk ='1' then
if hv_on_out_status = '0' then --hv_on to HVG HW interface
hv_on_out_status_d1 <= '0';
else
hv_on_out_status_d1 <= '1';
end if;
hv_on_out_status_d2 <= hv_on_out_status_d1;
end if;
end process;
-----------------------------------------------------
------generate HV generator reset pulse: 20ms--------
-----------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
hv_ret_out<='0';
hv_reg_reset<='0';
generate_ret<='0';
elsif sys_clk'event and sys_clk ='1' then
if hv_reset_com = '1' then -- slipring reset cmd pulse
generate_ret<='1';
elsif generate_ret='1' then
if delay20ms ="10101" then
hv_ret_out<='0';
generate_ret<='0';
hv_reg_reset<='0';
else
hv_ret_out<='1'; -- reset to HVG HW interface
hv_reg_reset<='1';
end if;
end if;
end if;
end process;
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
delay20ms <= "00000";
elsif sys_clk'event and sys_clk ='1' then
if generate_ret='1' then
if clk1ms_pulse='1' then
if delay20ms ="10101" then
delay20ms<="00000";
else
delay20ms<=delay20ms + '1';
end if;
end if;
else
delay20ms<="00000";
end if;
end if;
end process;
--------------------------------------------------------------
-------------Filter READY_logic_delay signal------------------
--------------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
READY_logic <= '0';
elsif sys_clk'event and sys_clk ='1' then
if READY = "111101111101011" then
-- if READY = "101101111101" then
READY_logic <= '1';
else
READY_logic <= '0';
end if;
end if;
end process;
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
READY_logic_delay1ms <= '0';
READY_logic_delay2ms <= '0';
READY_logic_delay3ms <= '0';
HV_fault_delay1ms <= '0';
HV_fault_delay2ms <= '0';
HV_fault_delay3ms <= '0';
HV_status_manual_del1ms <= '0';
HV_status_manual_del2ms <= '0';
hv_hss_h_speed_com1 <= '0';
hv_hss_h_speed_com2 <= '0';
hv_hss_h_speed_com3 <= '0';
starter_delay1ms <= '0';
starter_delay2ms <= '0';
starter_e_del2 <= '0';
starter_e_del1 <= '0';
make_data_delay1ms <= '0';
make_data_delay2ms <= '0';
elsif sys_clk'event and sys_clk ='1' then
if clk1ms_pulse='1' then
READY_logic_delay1ms<=READY_logic;
READY_logic_delay2ms<=READY_logic_delay1ms;
READY_logic_delay3ms<=READY_logic_delay2ms;
HV_status_manual_del1ms<=door_open_status;
HV_status_manual_del2ms<=HV_status_manual_del1ms;
HV_fault_delay1ms<=HV_fault_temp;
HV_fault_delay2ms<=HV_fault_delay1ms;
HV_fault_delay3ms<=HV_fault_delay2ms;
HV_fault_delay4ms<=HV_fault_delay3ms;
starter_delay1ms<=starter_status_in;
starter_delay2ms<=starter_delay1ms;
hv_hss_h_speed_com1 <= hss_h_speed_com;
hv_hss_h_speed_com2 <= hv_hss_h_speed_com1;
hv_hss_h_speed_com3 <= hv_hss_h_speed_com2;
starter_e_del1<=starter_e;
starter_e_del2<=starter_e_del1;
make_data_delay1ms<=make_data;
make_data_delay2ms<=make_data_delay1ms;
mdata_off_delay1ms <= mdata_off;
mdata_off_delay2ms <= mdata_off_delay1ms;
end if;
end if;
end process;
---------------------------------------------------------------
--------------maximal hv_on time is 100 seconds----------------
---------------------------------------------------------------
process(reset,sys_clk)
begin
if(reset=RESET_ACTIVE)then
max_exp_timer<=(others => '0');
max_exp_over<='0';
exposure_limit_time<='0';
elsif sys_clk'event and sys_clk ='1' then
if ETime_ref_pulse='1' then -- got exposure time from console
max_exp_timer<=(others => '0');
max_exp_over<='0';
exposure_limit_time<='0';
elsif (hv_on_out_status='1') and ( clk10ms_pulse='1') then
if max_exp_timer = "10011100010000" then --100s
max_exp_timer<=max_exp_timer;
max_exp_over<='1';
exposure_limit_time<='1';
else
max_exp_timer<=max_exp_timer+'1';
max_exp_over<='0';
exposure_limit_time<='0';
end if;
end if;
end if;
end process;
-----------------------------------------------------------
------hv_on signal disable when HVon load timer over-------
-----------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
exp_time_feed<=(others => '0');
HV_preset_timer<=(others => '0');
HVon_load_over<='1';
elsif sys_clk'event and sys_clk ='1' then
if hv_reset_com = '1' then
HVon_load_over<='0';
exp_time_feed<=(others => '0');
HV_preset_timer<=(others => '0');
else
if ETime_ref_pulse='1' then -- got exposure time from console
exp_time_feed<=(others => '0');
HV_preset_timer<=expo_time_ref; -- exposure time from console
HVon_load_over<='0';
else
if (hv_on_out_status='1') and ( clk10ms_pulse='1') then
if exp_time_feed = HV_preset_timer then
HV_preset_timer<=(others => '0');
HVon_load_over<='1'; -- exposure time over
else
exp_time_feed<=exp_time_feed +'1';
HVon_load_over<='0';
end if;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------
---------starter boost,run,brake and protection---------
--------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
counter_20_40min<=(others => '0');
counter<=(others => '0');
starter_on<='0';
boosting<='0';
braking<='0';
brake_flag<='0';
h_speed_warning <= '0';
hss_h_speed_sig <='1'; -- low
starter_self_off <= '0';
fsm_cnt <=(others => '0');
prt_status_stator<=idle;
elsif sys_clk'event and sys_clk='1' then
case prt_status_stator is
when idle=>
if starter_e_del3 ='1' then -- starter error fdbk from HVG DFD
starter_on <='0';
counter_20_40min<=(others => '0');
counter<=(others => '0');
hss_h_speed_sig <='1'; -- low
starter_self_off <= '1';
fsm_cnt <=x"01";
elsif (Starter_com_pulse='1' and starter_on_com ='1' and starter_on ='0') then -- console cmd: starter on
counter_20_40min<=(others => '0');
counter<=(others => '0');
starter_self_off <= '0';
if hss_h_speed_com = '0' then
hss_h_speed_sig <='0'; -- high
prt_status_stator<=wait_high_ready;
fsm_cnt <=x"02";
else
hss_h_speed_sig <='1'; -- low
prt_status_stator<=wait_low_ready;
fsm_cnt <=x"03";
end if;
-- elsif (hv_hss_h_speed_com3 ='1' and hv_hss_h_speed_com1 ='0' and starter_status_in ='1') then
elsif (hss_speed_pulse = '1' and hss_h_speed_com ='0' and starter_status_in ='1') then -- low speed to high speed cmd, boost
counter_20_40min<=(others => '0');
counter<=(others => '0');
starter_self_off <= '0';
hss_h_speed_sig <='0'; -- high
prt_status_stator<=wait_high_ready;
fsm_cnt <=x"04";
elsif (Starter_com_pulse='1' and starter_on_com ='0' and starter_on ='1') then -- console cmd: starter off
counter_20_40min<=(others => '0');
counter<=(others => '0');
starter_self_off <= '0';
if hv_hss_h_speed_stat = '1' then -- if starter is in H-speed, starter off cmd = brake to l_speed
brake_flag<='1';
hss_h_speed_sig <='1'; -- low
h_speed_warning <= '1'; --warning, receive starter off cmd when starter is in h_speed
prt_status_stator<=wait_brake_ready;
fsm_cnt <=x"05";
else
brake_flag<='0';
h_speed_warning <= '0';
prt_status_stator<=brake_status;
fsm_cnt <=x"06";
end if;
-- elsif (hv_hss_h_speed_com3 ='0' and hv_hss_h_speed_com1 ='1' and starter_status_in ='1') then
elsif (hss_speed_pulse = '1'and hss_h_speed_com ='1' and starter_status_in ='1') then -- high speed to low speed cmd, brake
counter_20_40min<=(others => '0');
counter<=(others => '0');
brake_flag<='1'; -- brake to low speed, do not turn off starter
hss_h_speed_sig <='1'; -- low
starter_self_off <= '0';
prt_status_stator<=wait_brake_ready;
fsm_cnt <=x"07";
elsif (Starter_com_pulse='1' and starter_on_com ='1' and starter_on ='1') then -- console cmd: starter on, already starter on
counter_20_40min<=(others => '0');
counter<=(others => '0');
starter_self_off <= '0';
prt_status_stator<=idle;
fsm_cnt <=x"08";
else
if hv_on_out_status='1' or starter_status_input1='0' then -- "FDBK: STARTER OFF " or "CMD: HV_ON to HVG HW"
counter_20_40min<=(others => '0');
starter_self_off <= '0';
prt_status_stator<=idle;
fsm_cnt <=x"09";
elsif pre_scan_flag = '1' then -- reset timer cmd, 20171205
counter_20_40min<=(others => '0');
starter_self_off <= '0';
prt_status_stator<=idle;
fsm_cnt <=x"A5";
else --"fdbk: starter already on" and "no HV_ON cmd/timerRst", which means system idle status.
if clk100ms_pulse ='1' then
if starter_off_mode = '1' then -- console cmd: turn starter off after 40mins
if counter_20_40min >= "0101110111000000" then -- l-speed for 40 minutes
counter_20_40min<=(others => '0');
counter<=(others => '0');
brake_flag<='0';
starter_self_off <= '1';
prt_status_stator<=brake_status;
fsm_cnt <=x"0a";
elsif counter_20_40min>="0001011101110000" and hv_hss_h_speed_stat = '1' then -- h-speed for 10 minutes
-- counter_20_40min<=(others => '0');
counter<=(others => '0');
brake_flag<='1'; -- brake to low speed, do not turn off starter
hss_h_speed_sig <='1'; -- low
starter_self_off <= '0';
prt_status_stator<=wait_brake_ready;
fsm_cnt <=x"0b";
else
counter_20_40min<=counter_20_40min +'1';
starter_self_off <= '0';
prt_status_stator<=idle;
fsm_cnt <=x"0c";
end if;
elsif starter_off_mode = '0' then -- console cmd: turn starter off after 20 mins
if counter_20_40min>="0001011101110000" and hv_hss_h_speed_stat = '1' then -- h-speed for 10 minutes
-- counter_20_40min<=(others => '0');
counter<=(others => '0');
brake_flag<='1'; -- brake to low speed, do not turn off starter
hss_h_speed_sig <='1'; -- low
starter_self_off <= '0';
prt_status_stator<=wait_brake_ready;
fsm_cnt <=x"0d";
elsif counter_20_40min>="0010111011100000" and hv_hss_h_speed_stat = '0' then -- l-speed for 20 minutes
counter_20_40min<=(others => '0');
counter<=(others => '0');
brake_flag<='0';
starter_self_off <= '1';
prt_status_stator<=brake_status;
fsm_cnt <=x"0e";
else
counter_20_40min<=counter_20_40min +'1';
prt_status_stator<=idle;
starter_self_off <= '0';
fsm_cnt <=x"0f";
end if;
end if;
end if;
end if;
end if;
when wait_high_ready =>
if hv_hss_h_speed_stat ='1' then -- HVG hight speed feedback
prt_status_stator<=boost_status;
fsm_cnt <=x"10";
else
prt_status_stator<=wait_high_ready;
fsm_cnt <=x"11";
end if;
when wait_low_ready =>
if hv_hss_h_speed_stat ='0' then -- HVG low speed feedback
prt_status_stator<=boost_status;
fsm_cnt <=x"12";
else
prt_status_stator<=wait_low_ready;
fsm_cnt <=x"13";
end if;
when wait_brake_ready =>
if hv_hss_h_speed_stat ='0' then -- HVG low speed feedback
prt_status_stator<=brake_status;
fsm_cnt <=x"14";
else
prt_status_stator<=wait_brake_ready;
fsm_cnt <=x"15";
end if;
when boost_status=>
if starter_e_del3 ='0' then -- no starter error fdbk from HVG DFD
starter_on<='1';
if clk100ms_pulse ='1' then
if counter=Boost_time then --18s boost time
counter<=(others => '0');
boosting<='0';
prt_status_stator<=idle;
fsm_cnt <=x"16";
else
counter<=counter +'1';
boosting<='1';
prt_status_stator<=boost_status;
fsm_cnt <=x"17";
end if;
else
boosting<='1';
prt_status_stator<=boost_status;
fsm_cnt <=x"18";
end if;
else -- starter error fdbk from HVG DFD
boosting<='0';
starter_on<='0';
counter<=(others => '0');
prt_status_stator<=idle;
fsm_cnt <=x"19";
end if;
when brake_status=>
starter_self_off <= '0';
if brake_flag='0' then -- brake
starter_on<='0';
fsm_cnt <=x"1a";
else -- slow down
starter_on<= starter_on;
fsm_cnt <=x"1b";
end if;
if starter_e_del3 ='0' then
if clk100ms_pulse ='1' then
if counter=Brake_time then --15s brake time
counter<=(others => '0');
braking<='0';
h_speed_warning <= '0';
brake_flag <= '0';
prt_status_stator<=idle;
fsm_cnt <=x"1c";
else
counter<=counter +'1';
braking<='1';
prt_status_stator<=brake_status;
fsm_cnt <=x"1d";
end if;
else
braking<='1';
prt_status_stator<=brake_status;
fsm_cnt <=x"1e";
end if;
else
braking<='0';
counter<=(others => '0');
prt_status_stator<=idle;
fsm_cnt <=x"1f";
end if;
when others =>
counter_20_40min<=(others => '0');
counter<=(others => '0');
h_speed_warning <= '0';
prt_status_stator<=idle;
fsm_cnt <=x"20";
end case;
end if;
end process;
-----------------------------------------------------
----------------filament protect---------------------
-----------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
fi_pro_pulse<='0';
count_100s<=(others => '0');
count_100ms<=(others => '0');
prt_status<=idle;
elsif sys_clk'event and sys_clk ='1' then
case prt_status is
when idle =>
if fila_host_data(11)= '1' then -- filament >= 3A
if hv_on_out_status_d1 = '1' then -- hv_on to HVG HW interface
count_100s<="0000000000";
count_100ms<=(others => '0');
prt_status<=idle;
elsif hv_on_out_status_d1 = '0' and hv_on_out_status_d2 = '1' then -- hv_on falling edge
count_100s<="0000000000";
count_100ms<=(others => '0');
prt_status<=count_100ms_status;
else -- system x-ray idle
if clk100ms_pulse='1' then
if count_100s(5 downto 3) ="111" then --5.6S
count_100s<="0000000000";
count_100ms<=(others => '0');
prt_status<=protect;
else
count_100s<=count_100s + '1';
prt_status<=idle;
end if;
else
prt_status<=idle;
end if;
end if;
else
count_100s<="0000000000";
count_100ms<=(others => '0');
prt_status<=idle;
end if;
when count_100ms_status =>
if (Fi_standby_mode ='0') or (READY_logic_delay ='0') then -- filament standby mode on HV not ready to scan, then 200ms set filament standby
if clk1ms_pulse='1' then
if hv_on_status_in = '0' then -- HVG feedback status: HV_OFF
count_100ms<=(others => '0');
prt_status<=protect;
elsif count_100ms="0011001000" then --200ms
count_100ms<=(others => '0');
prt_status<=protect;
else
count_100ms<=count_100ms + '1';
prt_status<=count_100ms_status;
end if;
else
prt_status<=count_100ms_status;
end if;
else -- if didn't enter to standby mode after expo,go back to idle
prt_status<=idle;
end if;
when protect =>
fi_pro_pulse<='1';
prt_status<=protect1;
when protect1 =>
fi_pro_pulse<='0';
if kv_ref_pulse ='1' then -- kV/mA/filament send EN
prt_status<=idle;
else
prt_status<=protect1;
end if;
when others=>
count_100s<=(others => '0');
count_100ms<=(others => '0');
prt_status<=idle;
end case;
end if;
end process;
-----------------------------------------
-----Filament limit(6A) protection-------
-----------------------------------------
-- process(reset,sys_clk)
--begin
-- if reset = RESET_ACTIVE then
-- fila_error_count <=( others => '0');
-- fila_error_flag<='0';
-- elsif sys_clk'event and sys_clk ='1' then
-- if hv_reset_com = '1' then --rise edge
-- fila_error_flag<='0';
-- fila_error_count <= ( others => '0');
-- else
-- if fila_fd_data >= "111101110110" then -- 5.8A
-- if clk1ms_pulse='1' then
-- if fila_error_count = "0011110" then -- 30ms
-- fila_error_count <= ( others => '0');
-- fila_error_flag<='1'; -- filament oc flag
-- else
-- fila_error_count <= fila_error_count + '1';
-- end if;
-- else
-- fila_error_flag<= fila_error_flag;
-- end if;
-- else
-- fila_error_count <= ( others => '0');
-- fila_error_flag<= fila_error_flag;
-- end if;
-- end if;
-- end if;
--end process;
----------------------------------------------------
------FIL_OFF cmd logic to HVG HW
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
-- fi_off_logic <='1';
fi_off_logic <='0'; -- 20170109
elsif sys_clk'event and sys_clk ='1' then
if fila_com_pulse='1' then
fi_off_logic<=fi_off_com;
elsif fila_error_flag='1' then -- close filament
-- fi_off_logic<='1';
fi_off_logic<='0'; -- 20170109
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------------
-----control hv_on signal, if timer is over or error occurs,then hv_on signal should be disabled-----
-----------------------------------------------------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
hv_on_out_status<='0';
elsif sys_clk'event and sys_clk='1' then
if hv_on_pulse='1' and hv_on_com='1' and (READY_logic_delay='1') and (timer_over = "00") then --console cmd:hv_on & system status ready for scan & not scanning
hv_on_out_status<='1'; -- hv_on to HVG HW interface
-- elsif (hv_on_com='0') or (timer_over/="00") or (READY_logic_delay='0') or (make_data_d2='0' and make_data_d1 ='1') or (Host_Abort_CMD='1') then -- make data falling edge
elsif (hv_on_com='0') or (timer_over/="00") or (READY_logic_delay='0') or (mdata_off_d2='0' and mdata_off_d1='1') or (Host_Abort_CMD='1') then -- make data over rising edge
hv_on_out_status<='0';
else
hv_on_out_status<=hv_on_out_status;
end if;
end if;
end process;
------------------------------------------------
-------HV exposure stop mode indication---------
------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
E_stop_mode<=(others => '0');
elsif sys_clk'event and sys_clk ='1' then
if hv_on_out_status='1' then -- hv_on to HVG HW interface
if hv_on_com='0' then -- console cmd: hv_off
E_stop_mode<="001";
elsif HVon_load_over='1' then -- exposure time over
E_stop_mode<="010";
elsif READY_logic_delay='0' then -- system status not ready for scan
E_stop_mode<="011";
-- elsif make_data_d1='0' and make_data_d2 ='1' then -- make data falling edge
elsif mdata_off_d2='0' and mdata_off_d1 ='1' then -- make data over rising edge
E_stop_mode<="100";
elsif Host_Abort_CMD='1' then
E_stop_mode<="101";
elsif max_exp_over ='1' then -- 100s
E_stop_mode<="110";
else
E_stop_mode<="000";
end if;
end if;
end if;
end process;
------------------------------------------------------------
---hv_off and report error when door is open during scan----
------------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
hv_fault_syn_temp<=HV_fault_status; -- fault from HVG DFD and hv_ctrl logic.
hv_fault_syn<=HV_fault_status;
door_status_in<='0';
prt_status_door<=idle;
elsif sys_clk'event and sys_clk ='1' then
if hv_reset_com = '1' then
hv_fault_syn<=HV_fault_status;
hv_fault_syn_temp<=HV_fault_status;
prt_status_door<=idle;
else
case prt_status_door is
when idle=>
if (hv_on_out_status ='1') then --hv_on to HVG HW interface
if HV_status_manual = '1' then -- door is open
hv_fault_syn<='1';
hv_fault_syn_temp<='1';
door_status_in<='1';
prt_status_door<=latch_err;
else
hv_fault_syn<=HV_fault_status;
hv_fault_syn_temp<=HV_fault_status;
prt_status_door<=idle;
end if;
else
hv_fault_syn<=HV_fault_status;
hv_fault_syn_temp<=HV_fault_status;
prt_status_door<=idle;
end if;
when latch_err=>
if HV_status_manual ='0' then
hv_fault_syn<=HV_fault_status;
hv_fault_syn_temp<=HV_fault_status;
door_status_in<='0';
prt_status_door<=idle;
else
hv_fault_syn<='1';
hv_fault_syn_temp<='1';
prt_status_door<=latch_err;
end if;
when others=>
hv_fault_syn<=HV_fault_status;
hv_fault_syn_temp<=HV_fault_status;
door_status_in<='0';
prt_status_door<=idle;
end case;
end if;
end if;
end process;
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
HV_fault_out<='0';
elsif sys_clk'event and sys_clk ='1' then
if hv_on_pulse='1' and hv_on_com='1' then
HV_fault_out<='0';
elsif hv_fault_syn_temp = '1' then
HV_fault_out<='1'; -- for status fdbk
end if;
end if;
end process;
-------------------------------------------------------
---------------generate 1ms pulse----------------------
-------------------------------------------------------
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
clk1ms_timer<=x"0000";
clk1ms_pulse<='0';
elsif sys_clk'event and sys_clk='1' then
if clk1ms_timer = x"9C3F" then
clk1ms_timer<=x"0000";
clk1ms_pulse<='1';
else
clk1ms_timer<=clk1ms_timer+'1';
clk1ms_pulse<='0';
end if;
end if;
end process;
--------------------------------------------------------
--generate 5ms pulse, test purpose
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
clk5ms_timer<="0000";
clk5ms_pulse<='0';
elsif sys_clk'event and sys_clk='1' then
if clk1ms_pulse='1'then
if clk5ms_timer = "0100" then
clk5ms_timer<="0000";
clk5ms_pulse<='1';
else
clk5ms_timer<=clk5ms_timer+'1';
clk5ms_pulse<='0';
end if;
else
clk5ms_pulse<='0';
end if;
end if;
end process;
---------------------------------------------------------
--generate 10ms pulse
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
clk10ms_timer<="0000";
clk10ms_pulse<='0';
elsif sys_clk'event and sys_clk='1' then
if clk1ms_pulse='1'then
if clk10ms_timer = "1001" then
clk10ms_timer<="0000";
clk10ms_pulse<='1';
else
clk10ms_timer<=clk10ms_timer+'1';
clk10ms_pulse<='0';
end if;
else
clk10ms_pulse<='0';
end if;
end if;
end process;
---------------------------------------------------------
--generate 100ms pulse
process(reset,sys_clk)
begin
if reset = RESET_ACTIVE then
clk100ms_timer<="0000000";
clk100ms_pulse<='0';
elsif sys_clk'event and sys_clk='1' then
if clk1ms_pulse='1'then
if clk100ms_timer = "1100011" then
clk100ms_timer<="0000000";
clk100ms_pulse<='1';
else
clk100ms_timer<=clk100ms_timer+'1';
clk100ms_pulse<='0';
end if;
else
clk100ms_pulse<='0';
end if;
end if;
end process;
----------------------------------------------------------
end Behavioral;
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