dsPIC33CH512MP508 FAMILY
48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers
with High-Resolution PWM and CAN Flexible Data (FD)
Operating Conditions
• 3V to 3.6V, -40°C to +125°C:
- Master: Up to 100 MIPS @ 200 MHz
- Slave: Up to 120 MIPS @ 240 MHz
Power Management
• Low-Power Management Modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
Core: Dual 16-Bit dsPIC33CH CPU
• Master/Slave Core Operation
• Independent Peripherals for Master Core and
Slave Core
• Configurable Shared Resources for Master Core
and Slave Core
• Master Core with 256-512 Kbytes of Program
Flash with ECC and 32-48K Data RAM with BIST
• Slave Core with 72 Kbytes of Program RAM
(PRAM) with ECC and 16K Data RAM with BIST
• Fast 6-Cycle Divide
• Live Update
• Message Boxes and FIFO to Communicate
Between Master and Slave (MSI)
• Code Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL Plus Hardware
Divide
• 32-Bit Multiply Support
• Five Sets of Interrupt Context Selected Registers
per Core for Fast Interrupt Response
• Zero Overhead Looping
High-Resolution PWM with Fine Edge
Placement
• Up to 12 PWM Channels:
- 4 channels for Master Core
- 8 channels for Slave Core
• 250 ps PWM Resolution
• Applications include:
- DC/DC Converters
- AC/DC power supplies
- Uninterruptable Power Supply (UPS)
- Motor control: BLDC, PMSM, SR, ACIM
Timers/Output Compare/Input Capture
• 2 General Purpose 16-Bit Timers:
- 1 each for Master and Slave cores
• Peripheral Trigger Generator (PTG) Module:
- 1 module for Master core
- Slave can interrupt on select PTG sources
- Useful for automating complex sequences
• 12 SCCP Modules:
- 8 modules for Master core
- 4 modules for Slave core
- Timer, Capture/Compare and PWM modes
- 16 or 32-bit time base
- 16 or 32-bit capture
- 4-deep capture buffer
- Fully asynchronous operation, available in
Sleep modes
Clock Management
• Internal Oscillator
• Programmable PLLs and Oscillator Clock
Sources
• Master Core Reference Clock Output
• Slave Core Reference Clock Output
• Fail-Safe Clock Monitor (FSCM)
• Fast Wake-up and Start-up
• Backup Internal Oscillator
• LPRC Oscillator
2017 Microchip Technology Inc.
Advance Information
DS70005308B-page 1
dsPIC33CH512MP508 FAMILY
Advanced Analog Features
• 4 ADC Modules:
- 1 module for Master core
- 3 modules for Slave core
- 12-bit, 4 Msps ADC
- Up to 18 conversion channels
- 250 ns conversion latency
- Capacitive Voltage Divider (CVD) for
touch sensing
• 4 DAC/Analog Comparator Modules:
- 1 module for Master core
- 3 modules for Slave core
- 12-bit DACs with hardware slope
compensation
- 15 ns analog comparators
• 3 PGA Modules:
- 3 modules for Slave core
- Can be read by Master Core ADC
• Shared DAC/Analog Output:
- DAC/analog comparator outputs
- PGA outputs
Direct Memory Access (DMA)
• 8 DMA Channels:
- 6 channels for Master core
- 2 channels for Slave core
Debugger Development Support
• In-Circuit and In-Application Programming
• Simultaneous Debugging Support for Master and
Slave
• Master Only Debug and Slave Only Debug
Support
• Master with 3 Complex, 5 Simple Breakpoints and
Slave with 1 Complex, 2 Simple Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace Buffer and Run-Time Watch
Safety Features
DMT (Deadman Timer)
ECC (Error Correcting Code)
WDT (Watchdog Timer)
CodeGuard™ Security with Flash PED (Program
Erase Disable)
• CRC (Cyclic Redundancy Check)
• RAM BIST (Built-In Self Test)
•
•
•
•
Communication Interfaces
• 3 UART Modules:
- 2 modules for Master core
- 1 module for Slave core
- Support for LIN/J2602 protocols and IrDA
®
• Three 4-Wire SPI/I
2
S Modules:
- 2 modules for Master core
- 1 module for Slave core
• 2 CAN Flexible Data (FD) Modules for the Master
Core
• 3 I
2
C Modules:
- 2 modules for Master core
- 1 module for Slave core
- Support for SMBus
• PPS to Allow Function Remap
• Programmable Cyclic Redundancy Check (CRC)
for the Master
• 2 SENT Modules for Master Core
DS70005308B-page 2
Advance Information
2017 Microchip Technology Inc.
dsPIC33CH512MP508 FAMILY
TABLE 1:
Core Frequency
Program Memory
Internal Data RAM
16-Bit Timer
DMA
SCCP (Capture/Compare/Timer)
UART
SPI/I
2
S
I
2
C
CAN FD
SENT
CRC
CVD
QEI
PTG
CLC
16-Bit High-Resolution PWM
12-Bit ADC
Digital Comparator
12-Bit DAC/Analog CMP Module
Watchdog Timer
Deadman Timer
Input/Output
Simple Breakpoints
PGAs
(1)
MASTER AND SLAVE CORE FEATURES
Feature
Master
100 MIPS @ 200 MHz
256-512 Kbytes
32-48 Kbytes
1
6
8
2
2
2
2
2
1
1
1
1
4
4
1
4
1
1
1
69
5
—
—
—
Slave owns the peripheral/feature, but it is shared with the Master.
Slave
120 MIPS @ 240 MHz
72 Kbytes (PRAM)
16 Kbytes
1
2
4
1
1
1
—
—
—
1
1
—
4
8
3
4
3
1
1
69
2
3
—
—
Shared
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
69
—
3
1
1
DAC Output Buffer
Oscillator
Note 1:
2017 Microchip Technology Inc.
Advance Information
DS70005308B-page 3
dsPIC33CH512MP50X/20X PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in
Table 2
and
Table 3.
The following pages show their pinout diagrams.
12-Bit DAC/Analog CMP
PWM (High Resolution)
Current Bias Source
ADC Channels
CVD Channels
ADC Modules
Flash/(PRAM)
16-Bit Timers
Data RAM
CAN FD
SPI/I
2
S
SCCP
UART
Product
Core
Devices with CAN FD
dsPIC33CH256MP505
dsPIC33CH512MP505
dsPIC33CH256MP506
dsPIC33CH512MP506
dsPIC33CH256MP508
dsPIC33CH512MP508
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
48
48
64
64
80
80
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
32K
16K
48K
16K
32K
16K
48K
16K
32K
16K
48K
16K
1
3
1
3
1
3
1
3
1
3
1
3
16
15
16
15
16
18
16
18
16
18
16
18
11
10
11
10
11
13
11
13
11
13
11
13
1
1
1
1
1
1
1
1
1
1
1
1
8
4
8
4
8
4
8
4
8
4
8
4
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
—
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
4
8
4
8
4
8
4
8
4
8
4
8
1
3
1
3
1
3
1
3
1
3
1
3
—
3
—
3
—
3
—
3
—
3
—
3
1
—
1
—
1
—
1
—
1
—
1
—
1
1
1
1
1
1
1
1
1
1
1
1
REFO
SENT
PGA
CRC
Pins
PTG
CLC
QEI
I
2
C
DS70005308B-page 4
dsPIC33CH512MP508 FAMILY
TABLE 2:
dsPIC33CH512MP508 MOTOR CONTROL/POWER SUPPLY FAMILIES
Advance Information
2017 Microchip Technology Inc.
2017 Microchip Technology Inc.
TABLE 3:
dsPIC33CH512MP208 MOTOR CONTROL/POWER SUPPLY FAMILIES WITH NO CAN FD
12-Bit DAC/Analog CMP
PWM (High Resolution)
Current Bias Source
1
—
1
—
1
—
1
—
1
—
1
—
ADC Channels
CVD Channels
ADC Modules
Flash/(PRAM)
16-Bit Timers
Data RAM
CAN FD
SPI/I
2
S
SCCP
UART
Product
Core
Devices with No CAN FD
dsPIC33CH256MP205
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
48
48
64
64
80
80
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
256K
(72K)
512K
(72K)
32K
16K
48K
16K
32K
16K
48K
16K
32K
16K
48K
16K
1
3
1
3
1
3
1
3
1
3
1
3
16
15
16
15
16
18
16
18
16
18
16
18
11
10
11
10
11
13
11
13
11
13
11
13
1
1
1
1
1
1
1
1
1
1
1
1
8
4
8
4
8
4
8
4
8
4
8
4
—
—
—
—
—
—
—
—
—
—
—
—
2
—
2
—
2
—
2
—
2
—
2
—
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
4
8
4
8
4
8
4
8
4
8
4
8
1
3
1
3
1
3
1
3
1
3
1
3
—
3
—
3
—
3
—
3
—
3
—
3
1
1
1
1
1
1
1
1
1
1
1
1
dsPIC33CH512MP205
dsPIC33CH256MP206
dsPIC33CH512MP206
dsPIC33CH256MP208
dsPIC33CH512MP208
REFO
SENT
PGA
CRC
Pins
PTG
CLC
QEI
I
2
C
Advance Information
DS70005308B-page 5
dsPIC33CH512MP508 FAMILY
