dsPIC33CK64MP105 FAMILY
16-Bit Digital Signal Controllers with High-Speed ADC, Op Amps,
Comparators and High-Resolution PWM
Operating Conditions
• 3.0V to 3.6V: -40°C to +125°C, DC to 100 MHz
Microcontroller Features
• Small Pin Count Packages Ranging from 28 to
48 Pins, Including UQFN as Small as 4x4 mm
• High-Current I/O Sink/Source
• Edge or Level Change Notification Interrupt on
I/O Pins
• Peripheral Pin Select (PPS) Remappable Pins
• Up to 64 Kbytes Flash Memory:
- 10,000 erase/write cycle endurance
- 20 years minimum data retention
- Self-programmable under software control
- Programmable code protection
- Error Code Correction (ECC)
- ICSP™ Write Inhibit
• Eight Kbytes SRAM Memory:
- SRAM Memory Built-In Self-Test (MBIST)
• Multiple Interrupt Vectors with Individually
Programmable Priority
• Four Sets of Interrupt Context Saving Registers
which Include Accumulator and STATUS for Fast
Interrupt Handling
• Four External Interrupt Pins
• Watchdog Timer (WDT)
• Windowed Deadman Timer (DMT)
• Fail-Safe Clock Monitor (FSCM) with Dedicated
Oscillator for Backup
• Selectable Oscillator Options Including:
- Low-Power 32 kHz RC (LPRC) Oscillator
- High-precision, 8 MHz internal Fast RC
(FRC) Oscillator
- Primary high-speed, crystal/resonator
oscillator or external clock
- Primary PLL, which can be clocked from FRC
or crystal oscillator
- Secondary/Alternate PLL (APLL) for PWM
and ADC
• Low-Power Management modes (Sleep and Idle)
• Power-on Reset and Brown-out Reset
• Programmable High/Low-Voltage Detect (HLVD)
• On-Board Capacitorless Regulator
• 256 Bytes of One-Time-Programmable (OTP)
Memory
High-Performance 16-Bit DSP RISC CPU
16-Bit Wide Data Path
Code Efficient (C and Assembly) Architecture
40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle, Mixed-Sign Multiply:
- 32-bit multiply support
• Fast 6-Cycle Divide
• Zero Overhead Looping
•
•
•
•
•
High-Speed PWM
•
•
•
•
•
•
Four PWM Pairs
Up to 250 ps PWM Resolution
Dead Time for Rising and Falling Edges
Dead-Time Compensation
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Fault and Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
High-Speed Analog-to-Digital Converter
• 12-Bit Resolution
• Two Dedicated SAR ADC Cores and One Shared
SAR ADC Core
• Up to 3.5 Msps Conversion Rate per Core
• Dedicated Result Buffer for Each Analog Channel
• Flexible and Independent ADC Trigger Sources
• Four Digital Comparators
• Four Oversampling Filters
2018-2019 Microchip Technology Inc.
DS70005363B-page 1
dsPIC33CK64MP105 FAMILY
Peripheral Features
• Three 4-Wire SPI modules (up to 50 Mbps):
- 16-byte FIFO
- Variable width
- I
2
S mode
• Two I
2
C Master and Slave w/Address Masking
and IPMI Support
• Three Protocol UARTs with Automated Handling
Support for:
- LIN 2.2
- DMX
- Smart card (ISO 7816)
- IrDA
®
• Two SENT modules
• One Dedicated 16-Bit Timer/Counter
• Four Single Output Capture/Compare/PWM/
Timer (SCCP) modules:
- Flexible configuration as PWM, input capture,
output compare or timers
- Two 16-bit timers or one 32-bit timer in each
module
- PWM resolution down to 4 ns
- Single PWM output
• One Multiple Output Capture/Compare/PWM/
Timer (MCCP) module:
- Flexible configuration as PWM, input capture,
output compare or timers
- Two 16-bit timers or one 32-bit timer in each
module
- PWM resolution down to 4 ns
- Up to six PWM outputs
- Programmable dead time
- Auto-shutdown
• Two Quadrature Encoder Interfaces (QEI):
- Four inputs: Phase A, Phase B, Home, Index
• Reference Clock Output (REFCLKO)
• Four Configurable Logic Cells (CLC) with Internal
Connections to Select Peripherals and PPS
• 4-Channel Hardware DMA
• 32-Bit CRC Calculation module
• Peripheral Trigger Generator (PTG):
- 16 possible trigger sources to other
peripheral modules
- CPU independent state machine-based
instruction sequencer
Analog Features
• Three Fast Analog Comparators with
Input Multiplexing
• Three Operational Amplifiers
• Three 12-Bit PDM DACs with
Slope Compensation
• One Output DAC Buffer
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
• Class B Safety Library, IEC 60730
Debug Features
• Three Programming and Debugging Interfaces:
- 2-wire ICSP™ interface with non-intrusive
access and real-time data exchange with
application
• Three Complex, Five Simple Breakpoints
• IEEE Standard 1149.2 Compatible (JTAG)
Boundary Scan
DS70005363B-page 2
2018-2019 Microchip Technology Inc.
dsPIC33CK64MP105 PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in
Table 1.
The following pages show their pinout diagrams.
12-Bit ADC (External Channels)
High-Speed PWM (Generators)
General Purpose I/O/PPS
Dedicated 16-Bit Timers
Program Memory
DMA (Channels)
Op Amplifiers
Data Memory
Comparators
12-Bit DACs
MCCP
(1)
SCCP
(2)
SPI/I
2
S
UARTs
32-Bit CRC
Product
CLC
2018-2019 Microchip Technology Inc.
DS70005363B-page 3
TABLE 1:
dsPIC33CK64MP105 FAMILY
Remappable Peripherals
SENT
Pins
QEI
I
2
C
Packages
dsPIC33CK64MP105 FAMILY
dsPIC33CK32MP102
dsPIC33CK32MP103
dsPIC33CK32MP105
dsPIC33CK64MP102
dsPIC33CK64MP103
dsPIC33CK64MP105
Note 1:
2:
28
36
48
28
36
48
32K
32K
32K
64K
64K
64K
8K
8K
8K
8K
8K
8K
21/16
27/22
39/34
21/16
27/22
39/34
4
4
4
4
4
4
12
16
19
12
16
19
1
1
1
1
1
1
3
3
3
3
3
3
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
2
3
3
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
4
4
4
4
4
4
SSOP/UQFN
UQFN
UQFN/TQFP
SSOP/UQFN
UQFN
UQFN/TQFP
MCCP can be configured as a PWM with up to six outputs, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer.
SCCP can be configured as a PWM with one output, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer.
dsPIC33CK64MP105 FAMILY
Pin Diagrams
28-Pin SSOP
(1)
RA1
RA2
RA3
RA4
AV
DD
AV
SS
V
DD
V
SS
RB0
RB1
(2,4)
RB2
RB3
RB4
RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RA0
MCLR
RB15
RB14
RB13
RB12
RB11
RB10
(3)
V
DD
V
SS
RB9
RB8
RB7
RB6
= 5V Tolerant
Note 1:
2:
3:
4:
See
Table 2
for a complete description of pin functions.
Pin has an increased current drive strength. Refer to
Section 31.0 “Electrical Characteristics”
for details.
A pull-up resistor is connected to this pin during programming or when JTAG is enabled in the Configuration bits.
This pin is toggled during programming.
TABLE 2:
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note 1:
2:
3:
4:
28-PIN SSOP COMPLETE PIN FUNCTION DESCRIPTIONS
Function
(1)
Pin #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PGC3/RP38/SCL2/RB6
TDO/AN2/CMP3A/RP39/RB7
PGD1/AN10/RP40/SCL1/RB8
PGC1/AN11/RP41/SDA1/RB9
V
SS
V
DD
TMS/RP42/PWM3H/RB10
(3)
TCK/RP43/PWM3L/RB11
TDI/RP44/PWM2H/RB12
RP45/PWM2L/RB13
RP46/PWM1H/RB14
RP47/PWM1L/RB15
MCLR
OA1OUT/AN0/CMP1A/IBIAS0/RA0
Function
(1)
OA1IN-/ANA1/RA1
OA1IN+/AN9/RA2
DACOUT/AN3/CMP1C/RA3
AN4/CMP3B/IBIAS3/RA4
AV
DD
AV
SS
V
DD
V
SS
OSCI/CLKI/AN5/RP32/RB0
OSCO/CLKO/AN6/RP33/RB1
(2,4)
OA2OUT/AN1/AN7/ANA0/CMP1D/CMP2A/CMP3D/RP34/INT0/
RB2
PGD2/OA2IN-/AN8/RP35/RB3
PGC2/OA2IN+/RP36/RB4
PGD3/RP37/SDA2/RB5
RPn
represents remappable peripheral functions.
Pin has an increased current drive strength. Refer to
Section 31.0 “Electrical Characteristics”
for details.
A pull-up resistor is connected to this pin during programming or when JTAG is enabled in the Configuration bits.
This pin is toggled during programming.
dsPIC33CKXXMP102
DS70005363B-page 4
2018-2019 Microchip Technology Inc.
dsPIC33CK64MP105 FAMILY
Pin Diagrams (Continued)
28-Pin UQFN
(1)
RB10
(3)
RB13
RB12
RB11
RB9
= 5V Tolerant
V
DD
28 27 26 25 24 23 22
RB14
RB15
MCLR
RA0
RA1
RA2
RA3
1
2
3
5
6
7
8 9 10 11 12 13 14
AV
SS
RA4
AV
DD
V
DD
V
SS
RB0
RB1
(2,4)
21
20
19
17
16
15
RB8
RB7
RB6
RB5
RB4
RB3
RB2
4
dsPIC33CKXXMP102
18
Note 1:
2:
3:
4:
See
Table 3
for a complete description of pin functions.
Pin has an increased current drive strength. Refer to
Section 31.0 “Electrical Characteristics”
for details.
A pull-up resistor is connected to this pin during programming or when JTAG is enabled in the Configuration bits.
This pin is toggled during programming.
TABLE 3:
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note 1:
2:
3:
4:
28-PIN UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Function
(1)
Pin #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
(1)
OA2OUT/AN1/AN7/ANA0/CMP1D/CMP2D/CMP3D/RP34/INT0/RB2
PGD2/OA2IN-/AN8/RP35/RB3
PGC2/OA2IN+/RP36/RB4
PGD3/RP37/SDA2/RB5
PGC3/RP38/SCL2/RB6
TDO/AN2/CMP3A/RP39/RB7
PGD1/AN10/RP40/SCL1/RB8
PGC1/AN11/RP41/SDA1/RB9
V
SS
V
DD
TMS/RP42/PWM3H/RB10
(3)
TCK/RP43/PWM3L/RB11
TDI/RP44/PWM2H/RB12
RP45/PWM2L/RB13
RP46/PWM1H/RB14
RP47/PWM1L/RB15
MCLR
OA1OUT/AN0/CMP1A/IBIAS0/RA0
OA1IN-/ANA1/RA1
OA1IN+/AN9/RA2
DACOUT/AN3/CMP1C/RA3
AN4/CMP3B/IBIAS3/RA4
AV
DD
AV
SS
V
DD
V
SS
OSCI/CLKI/AN5/RP32/RB0
OSCO/CLKO/AN6/RP33/RB1
(2,4)
RPn
represents remappable peripheral functions.
Pin has an increased current drive strength. Refer to
Section 31.0 “Electrical Characteristics”
for details.
A pull-up resistor is connected to this pin during programming or when JTAG is enabled in the Configuration bits.
This pin is toggled during programming.
2018-2019 Microchip Technology Inc.
V
SS
DS70005363B-page 5
