LDO Regulator, 150 mA,
38 V, 1
mA
I
Q
, with PG
NCP730
The NCP730 device is based on unique combination of features
−
very low quiescent current, fast transient response and high input and
output voltage ranges. The NCP730 is CMOS LDO regulator designed
for up to 38 V input voltage and 150 mA output current. Quiescent
current of only 1
mA
makes this device ideal solution for battery−
powered, always−on systems. Several fixed output voltage versions
are available as well as the adjustable version.
The device (version B) implements power good circuit (PG) which
indicates that output voltage is in regulation. This signal could be used
for power sequencing or as a microcontroller reset.
Internal short circuit and over temperature protections saves the
device against overload conditions.
Features
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MARKING DIAGRAMS
TSOP−5
SN SUFFIX
CASE 483
5
XXXAYWG
G
5
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 2.7 V to 38 V
Output Voltage: 1.2 V to 24 V
Capable of Sourcing 200 mA Peak Output Current
Very Low Quiescent Current: 1
mA
typ.
Low Dropout: 290 mV typ. at 150 mA, 3.3 V Version
Output Voltage Accuracy
±1%
Power Good Output (Version B)
Stable with Small 1
mF
Ceramic Capacitors
Built−in Soft Start Circuit to Suppress Inrush Current
Over−Current and Thermal Shutdown Protections
Available in Small TSOP−5 and WDFN6 (2x2) Packages
These Devices are Pb−Free and are RoHS Compliant
Battery Power Tools and Equipment
Home Automation
RF Devices
Metering
Remote Control Devices
White Goods
1
XXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
WDFN6 (2x2)
MT SUFFIX
CASE 511BR
1
1
XX M
XX = Specific Device Code
M = Date Code
PIN ASSIGNMENTS
TSOP−5
IN
GND
EN
1
2
3
4
NC/ADJ/PG
5
OUT
Typical Applications
CASE 483
WDFN6 (2x2)
OUT 1
NC/ADJ 2
GND 3
EP
6 IN
5 NC/PG
4 EN
CASE511BR
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 29 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2018
March, 2021
−
Rev. 1
1
Publication Order Number:
NCP730/D
NCP730
TYPICAL APPLICATION SCHEMATICS
V
IN
=6−38V
C
IN
1mF
ON
OFF
V
OUT
=5.0V
C
OUT
1mF
V
IN
=6−38V
C
IN
1mF
V
OUT
=5V
R1
2M4
1.2V
R2
750k
C
FF
1nF
C
OUT
1mF
IN
OUT
IN
OUT
NCP730A 5.0V
TSOP−5 / WDFN−6
EN
GND
NC
ON
OFF
NCP730A ADJ
TSOP−5 / WDFN−6
EN
GND
ADJ
Figure 1. Fixed Output Voltage Application (No PG)
Figure 2. Adjustable Output Voltage Application (No PG)
V
IN
=6−38V
C
IN
1mF
ON
IN
OUT
V
OUT
=5.0V
C
OUT
1mF
V
IN
=6−38V
C
IN
1mF
ON
IN
OUT
NCP730B ADJ
Only WDFN−6
1.2V
ADJ
R1
2M4
C
FF
1nF
V
OUT
=5V
C
OUT
1mF
R
PG
100k
NCP730B 5.0V
TSOP−5 / WDFN−6
NC
EN
OFF
GND
PG
R
PG
100k
PG
EN
OFF
GND
PG
R2
750k
PG
Figure 3. Fixed Output Voltage Application with PG
Figure 4. Adjustable Output Voltage Application with PG
V
OUT
+
V
ADJ
@
1
)
R
1
)
I
ADJ
@
R
1
R
2
IN
UVLO
1.95 V
I
EN−PU
= 300nA
V
CCEN
V−REFERENCE
AND SOFT−START
V
REF
1.2V
EA
R
ADJ1
V
FB
=1.2V
Enable
EN Comparator
0.9 V
THERMAL
SHUTDOWN
R
ADJ2
Current limit
UVLO Comparator
OUT
EN
ADJ
GND
PG Comparator
DEGLITCH
DELAY TMR
PG
NC
93% of V
REF
Note:
Blue objects are valid for ADJ version
Green objects are valid for FIX version
Brown objects are valid for B version (with PG)
Figure 5. Internal Block Diagram
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2
NCP730
PIN DESCRIPTION
−
TSOP−5 package
Pin No.
1
2
3
4
Pin Name
IN
GND
EN
ADJ/PG/NC
Power supply input pin.
Ground pin.
Enable input pin (high
−
enabled, low
−
disabled). If this pin is connected to IN pin or if it is left uncon-
nected (pull−up resistor is not required) the device is enabled.
ADJ (ADJ device version only):
•
Adjust input pin. Could be connected to the output resistor divider or to the output pin directly.
PG (FIX device versions with PG functionality):
•
Power good output pin. High level for power ok, low level for fail. If not used, could be left
unconnected or shorted to GND.
NC (FIX device versions without PG functionality):
•
Not internally connected. This pin can be tied to the ground plane to improve thermal dissipation.
Output pin.
Description
5
OUT
PIN DESCRIPTION
−
WDFN−6 package
Pin No.
1
2
Pin Name
OUT
NC/ADJ
Output pin.
ADJ (ADJ device version only):
•
Adjust input pin. Could be connected to the output resistor divider or to the output pin directly.
NC (all FIX device versions):
•
Not internally connected. This pin can be tied to the ground plane to improve thermal dissipation.
Ground pin.
Enable input pin (high
−
enabled, low
−
disabled). If this pin is connected to IN pin or if it is left
unconnected (pull−up resistor is not required) the device is enabled.
PG (ADJ/FIX device versions with PG functionality):
•
Power good output pin. High level for power ok, low level for fail. If not used, could be left
unconnected or shorted to GND.
NC (ADJ/FIX device versions without PG functionality):
•
Not internally connected. This pin can be tied to the ground plane to improve thermal dissipation.
Power supply input pin.
Exposed pad pin. Should be connected to the GND plane.
Description
3
4
5
GND
EN
NC/PG
6
EP
IN
EPAD
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3
NCP730
MAXIMUM RATINGS
Rating
VIN Voltage (Note 1)
VOUT Voltage
EN Voltage
ADJ Voltage
PG Voltage
Output Current
PG Current
Maximum Junction Temperature
Storage Temperature
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Symbol
V
IN
V
OUT
V
EN
V
FB/ADJ
V
PG
I
OUT
I
PG
T
J(MAX)
T
STG
ESD
HBM
ESD
CDM
Value
−0.3
to 40
−0.3
to [(V
IN
+ 0.3) or 40 V; whichever is lower]
−0.3
to (V
IN
+ 0.3)
−0.3
to 5.5
−0.3
to (V
IN
+ 0.3)
Internally limited
3
150
−55
to 150
2000
1000
Unit
V
V
V
V
V
mA
mA
°C
°C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101
THERMAL CHARACTERISTICS
(Note 3)
Characteristic
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case (top)
Thermal Resistance, Junction−to−Case (bottom)
Thermal Resistance, Junction−to−Board (top)
Thermal Characterization Parameter, Junction−to−Case (top)
Thermal Characterization Parameter, Junction−to−Board [FEM]
Symbol
R
thJA
R
thJCt
R
thJCb
R
thJBt
Psi
JCt
Psi
JB
WDFN6 2x2
61
200
14
46
3
46
TSOP−5
142
80
N/A
110
21
113
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
3. Measured according to JEDEC board specification (board 1S2P, Cu layer thickness 1 oz, Cu area 650 mm
2
, no airflow). Detailed description
of the board can be found in JESD51−7.
ELECTRICAL CHARACTERISTICS
(V
IN
= V
OUT−NOM
+ 1 V and V
IN
≥
2.7 V, V
EN
= 1.2 V, I
OUT
= 1 mA, C
IN
= C
OUT
= 1.0
mF
(effective capacitance – Note 4), T
J
=
−40°C
to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 5)
Parameter
Recommended Input Voltage
Output Voltage Accuracy
ADJ Reference Voltage
ADJ Input Current
Line Regulation
Load Regulation
Quiescent Current (version A)
Quiescent Current (version B)
Ground Current
Shutdown Current (Note 9)
Output Current Limit
Short Circuit Current
Dropout Voltage (Note 6)
Power Supply Ripple Rejection
T
J
=
−40°C
to +85°C
T
J
=
−40°C
to +125°C
ADJ version only
V
ADJ
= 1.2 V
V
IN
= V
OUT−NOM
+ 1 V to 38 V and V
IN
≥
2.7 V
I
OUT
= 0.1 mA to 150 mA
V
IN
= V
OUT−NOM
+ 1 V to 38 V, I
OUT
= 0 mA
V
IN
= V
OUT−NOM
+ 1 V to 38 V, I
OUT
= 0 mA
I
OUT
= 150 mA
V
EN
= 0 V, I
OUT
= 0 mA, V
IN
= 38 V
V
OUT
= V
OUT−NOM
−
100 mV
V
OUT
= 0 V
I
OUT
= 150 mA
V
IN
= V
OUT−NOM
+ 2 V
I
OUT
= 10 mA
10 Hz
10 kHz
I
GND
I
SHDN
I
OLIM
I
OSC
V
DO
PSRR
V
ADJ
I
ADJ
DV
O(DVI)
DV
O(DIO)
I
Q
Test Conditions
Symbol
V
IN
V
OUT
Min
2.7
−1
−1
−
−0.1
−
−
−
−
−
−
200
200
−
−
−
Typ
−
−
−
1.2
0.01
−
−
1.3
1.8
325
0.35
280
280
290
80
70
Max
38
1
2
−
0.1
0.2
0.4
2.5
3.0
450
1.5
450
450
480
−
−
mA
mA
mA
mA
mV
dB
V
mA
%V
OUT
%V
OUT
mA
Unit
V
%
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4
NCP730
ELECTRICAL CHARACTERISTICS
(V
IN
= V
OUT−NOM
+ 1 V and V
IN
≥
2.7 V, V
EN
= 1.2 V, I
OUT
= 1 mA, C
IN
= C
OUT
= 1.0
mF
(effective capacitance – Note 4), T
J
=
−40°C
to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 5) (continued)
Parameter
Power Supply Ripple Rejection
Output Voltage Noise
Test Conditions
V
IN
= V
OUT−NOM
+ 2 V
I
OUT
= 10 mA
f = 10 Hz to 100 kHz
100 kHz
1 MHz
FIX−3.3 V
FIX−5.0 V
FIX−15.0 V
ADJ set to 5.0 V
C
FF
= 100 pF
ADJ set to 5.0 V
C
FF
= 10 nF
EN Threshold
EN Hysteresis
EN Internal Pull−up Current
EN Input Leakage Current
Start−up time (Note 7)
Internal UVLO Threshold
Internal UVLO Hysteresis
PG Threshold (Note 8)
PG Hysteresis (Note 8)
PG Deglitch Time (Note 8)
PG Delay Time (Note 8)
PG Output Low Level Voltage (Note 8) I
PG
= 1 mA
PG Output Leakage Current (Note 8)
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
V
PG
= 30 V
Temperature rising from T
J
= +25°C
Temperature falling from T
SD
V
EN
rising
V
EN
falling
V
EN
= 1 V, V
IN
= 5.5 V
V
EN
= 30 V, V
IN
= 30 V
V
OUT−NOM
≤
3.3 V
V
OUT−NOM
> 3.3 V
Ramp V
IN
up until output is turned on
Ramp V
IN
down until output is turned off
V
OUT
falling
V
OUT
rising
V
IUL−TH
V
IUL−HY
V
PG−TH
V
PG−HY
t
PG−DG
t
PG−DLY
V
PG−OL
I
PG−LK
T
SD
T
SDH
V
EN−TH
V
EN−HY
I
EN−PU
I
EN−LK
t
START
V
N
Symbol
PSRR
Min
−
−
−
−
−
−
−
0.7
0.01
0.01
−1
100
300
1.6
0.05
90
0.1
75
120
−
−
−
−
Typ
42
48
195
240
460
132
82
0.9
0.1
0.3
0.05
250
600
1.95
0.2
93
2
160
320
0.2
0.01
165
20
Max
−
−
−
−
−
−
−
1.05
0.2
1
1
500
1000
2.6
0.3
96
4
270
600
0.4
1
−
−
V
V
%
%
ms
ms
V
mA
°C
°C
V
V
mA
mA
ms
mV
RMS
Unit
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T
A
= 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
6. Dropout measured when the output voltage falls 100 mV below the nominal output voltage. Limits are valid for all voltage versions.
7. Startup time is the time from EN assertion to point when output voltage is equal to 95% of V
OUT−NOM
.
8. Applicable only to version B (device option with power good output). PG threshold and PG hysteresis are expressed in percentage of nominal
output voltage.
9. Shutdown current includes EN Internal Pull−up Current.
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5
