DATA SHEET
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High Speed Low Power
CAN, CAN FD Transceiver
8
MARKING
DIAGRAM
8
1
SOIC−8 NB
CASE 751−07
1
1
NV7344xy
ALYWG
G
NV7344xy
ALYW
G
G
NCV7344
Description
The NCV7344 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7344 is an addition to the CAN high−speed transceiver
family complementing NCV734x CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
The NCV7344 guarantees additional timing parameters to ensure
robust communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7344 an excellent choice for all types of HS−CAN networks, in
nodes that require a low−power mode with wake−up capability via the
CAN bus.
Features
1
DFN8
MW SUFFIX
CASE 507AB
•
Compatible with ISO 11898−2:2016
•
Specification for Loop Delay Symmetry up to 5 Mbps
•
V
IO
pin on NCV7344−3 Version Allowing Direct Interfacing with
•
•
•
•
•
•
•
•
•
•
•
NV7344xy= Specific Device Code
x =
−
or A
y = 0 or 3
−
= long filter time
A = short filter time
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
3 V to 5 V Microcontrollers
Very Low Current Standby Mode with Wake−up via the Bus
Low Electromagnetic Emission (EME) and High Electromagnetic
Immunity
Very Low EME without Common−mode (CM) Choke
No Disturbance of the Bus Lines with an Un−powered Node
Transmit Data (TxD) Dominant Timeout Function
Under All Supply Conditions the Chip Behaves Predictably
Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses
Thermal Protection
Bus Pins Short Circuit Proof to Supply Voltage and Ground
Bus Pins Protected Against Transients in an Automotive
Environment
These are Pb−free Devices
PIN ASSIGNMENT
TxD
GND
V
CC
RxD
NCV7344D1x
(Top View)
TxD
GND
V
CC
RxD
STB
CANH
CANL
NC
(−0)
V
IO (−3)
EP Flag
NCV7344MWx
(Top View)
STB
CANH
CANL
NC
(−0)
V
IO (−3)
Quality
•
Wettable Flank Package for Enhanced Optical Inspection
•
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Typical Applications
•
Automotive
•
Industrial Networks
©
Semiconductor Components Industries, LLC, 2017
August, 2021
−
Rev. 4
1
Publication Order Number:
NCV7344/D
NCV7344
BLOCK DIAGRAM
NC
5
V
CC
V
CC
3
NCV7344−0
Thermal
shutdown
Timer
7
CANH
TxD
1
V
CC
STB
8
Mode &
Wake−up
control
Driver control
6
CANL
RxD
4
Wake−up
Filter
COMP
GND
2
COMP
Figure 1. NCV7344−0 Block Diagram
V
IO
5
V
IO
V
CC
3
NCV7344−3
Thermal
shutdown
Timer
7
CANH
TxD
1
V
IO
STB
8
Mode &
Wake−up
control
Driver control
6
CANL
RxD
GND
4
Wake−up
Filter
COMP
2
COMP
Figure 2. NCV7344−3 Block Diagram
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2
NCV7344
TYPICAL APPLICATION
VBAT
IN
5V
−reg
OUT
V
CC
NC
5
3
7
V
CC
R
LT
= 60
W
CANH
CAN
BUS
CANL
R
LT
= 60
W
STB
8
NCV7344
Micro−
controller
TxD
1
RxD
4
6
2
GND
GND
Figure 3. Application Diagram NCV7344−0
VBAT
IN
5V
−reg
OUT
IN
3V
−reg
OUT
V
IO
5
3
7
V
CC
R
LT
= 60
W
CANH
CAN
BUS
CANL
R
LT
= 60
W
STB
8
NCV7344−
3
Micro−
controller
TxD
1
RxD
4
6
2
GND
GND
Figure 4. Application Diagram NCV7344−3
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
5
6
7
8
Name
TxD
GND
V
CC
RxD
NC
V
IO
CANL
CANH
STB
EP
Ground
Supply voltage
Receive data output; dominant transmitter
Ù
low output
Not connected. On NCV7344−0 only
Digital Input / Output pins and other functions supply voltage. On NCV7344−3 only
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Standby mode control input; internal pull−up current
Exposed Pad. Recommended to connect to GND or left floating in application (DFN8 package only).
Description
Transmit data input; low input
Ù
dominant driver; internal pull−up current
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NCV7344
FUNCTIONAL DESCRIPTION
Operating Modes
Overtemperature Detection
NCV7344 provides two modes of operation as illustrated
in Table 2. These modes are selectable through pin STB.
Table 2. OPERATING MODES
Pin STB
Low
High
Mode
Normal
Standby
Low when bus
dominant
Follows the bus
when wake−up
detected
Pin RxD
High when bus
recessive
High when no
wake−up
request detected
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 180°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
TxD Dominant Timeout Function
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are biased to ground and supply current is reduced to a
minimum, typically 10
mA.
When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of t
wake_filt
, the RxD pin is driven low by the
transceiver (following the bus) to inform the controller of
the wake−up request.
Wake−up
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant timeout time t
dom(TxD)
defines
the minimum possible bit rate to 17 kbps.
Fail Safe Features
When a valid wake−up pattern (phase in order
dominant – recessive – dominant) is detected during the
standby mode the RxD pin follows the bus. Minimum length
of each phase is t
wake_filt
– see Figure 5.
Pattern must be received within t
wake_to
to be recognized
as valid wake−up otherwise internal logic is reset.
t
wake_filt
CANH
CANL
t
wake_filt
t
wake_filt
< t
wake_to
RxD
t
dwakerd
t
dwakedr
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Standby undervoltage on VCC pin prevents the chip
sending data on the bus when there is not enough VCC
supply voltage by entering standby mode. Undervoltage
detection on VIO pin (NCV7344−3 version only) also
causes transition to standby mode. Switch−off undervoltage
detection level on supply pin(s) forces transceiver to
disengage from the bus until the supply is recovered. After
supply is recovered TxD pin must be first released to high to
allow sending dominant bits again. Recovery time from
undervoltage detection is equal to td(stb−nm) time.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 7). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
The V
IO
pin (available only on NCV7344−3 version)
should be connected to microcontroller supply pin. By using
V
IO
supply pin shared with microcontroller the I/O levels
between microcontroller and transceiver are properly
adjusted. See Figure 4. Pin V
IO
also provides the internal
supply voltage for low−power differential receiver of the
transceiver. This allows detection of wake−up request even
when there is no supply voltage on pin V
CC
.
V
IO
Supply Pin
Figure 5. NCV7344 Wake−up Behavior
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NCV7344
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
ABSOLUTE MAXIMUM RATINGS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
V
SUP
V
CANH
V
CANL
V
CANH−CANL
V
I/O
V
esdHBM
V
esdCDM
V
esdIEC
V
schaff
Parameter
Supply voltage V
CC
, V
IO
DC voltage at pin CANH
DC voltage at pin CANL
DC voltage between CANH and CANL
DC voltage at pin TxD, RxD, STB
Electrostatic discharge voltage at all pins,
Component HBM
Electrostatic discharge voltage at all pins,
Component CDM
Electrostatic discharge voltage at pins CANH and
CANL, System HBM (Note 4)
Voltage transients, pins CANH, CANL. According
to ISO7637−3, Class C (Note 4)
(Note 1)
(Note 2)
(Note 3)
test pulses 1
test pulses 2a
test pulses 3a
test pulses 3b
Latch−up
T
stg
T
J
Static latch−up at all pins
Storage temperature
Maximum junction temperature
(Note 5)
−55
−40
−150
+100
150
+150
+170
0 < V
CC
< 5.25 V; no time limit
0 < V
CC
< 5.25 V; no time limit
Conditions
Min
−0.3
−42
−42
−42
−0.3
−8
−750
−8
−100
+75
Max
+6
+42
+42
+42
+6
+8
+750
+8
Unit
V
V
V
V
V
kV
V
kV
V
V
V
V
mA
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011
3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330
W
resistor referenced to GND.
4. Results were verified by external test house.
5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
Table 4. THERMAL CHARACTERISTICS
Parameter
Thermal characteristics, SOIC−8 (Note 6)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8)
Thermal characteristics, DFN8 (Note 6)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8)
Symbol
R
qJA
R
qJA
R
qJA
R
qJA
Value
131
81
125
58
Unit
°C/W
°C/W
°C/W
°C/W
6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
7. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
8. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
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