2016.02.11
Arria 10 Device Overview
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A10-OVERVIEW
The Arria
®
10 device family consists of high-performance and power-efficient 20 nm mid-range FPGAs
and SoCs.
Arria 10 device family delivers:
• Higher performance than the previous generation of mid-range and high-end FPGAs.
• Power efficiency attained through a comprehensive set of power-saving technologies.
The Arria 10 devices are ideal for high performance, power-sensitive, midrange applications in diverse
markets.
Table 1: Sample Markets and Ideal Applications for Arria 10 Devices
Market
Applications
Wireless
Wireline
• Channel and switch cards in remote radio heads
• Mobile backhaul
•
•
•
•
•
•
•
•
40G/100G muxponders and transponders
100G line cards
Bridging
Aggregation
Studio switches
Servers and transport
Videoconferencing
Professional audio and video
Broadcast
Computing and Storage
• Flash cache
• Cloud computing servers
• Server acceleration
• Diagnostic scanners
• Diagnostic imaging
Medical
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2
Key Advantages of Arria 10 Devices
A10-OVERVIEW
2016.02.11
Market
Applications
Military
•
•
•
•
Missile guidance and control
Radar
Electronic warfare
Secure communications
Related Information
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the
Arria 10 Device Handbook
chapters.
Key Advantages of Arria 10 Devices
Table 2: Key Advantages of the Arria 10 Device Family
Advantage
Supporting Feature
Enhanced core architecture
• Built on TSMC's 20 nm process technology
• 60% higher performance than the previous generation of mid-
range FPGAs
• 15% higher performance than the fastest previous-generation
FPGA
• Short-reach rates up to 25.8 Gigabits per second (Gbps)
• Backplane capability up to 17.4 Gbps
• Integrated 10GBASE-KR and 40GBASE-KR4 Forward Error
Correction (FEC)
•
•
•
•
•
•
8-input adaptive logic module (ALM)
Up to 65.6 megabits (Mb) of embedded memory
Variable-precision digital signal processing (DSP) blocks
Fractional synthesis phase-locked loops (PLLs)
Hard PCI Express Gen3 IP blocks
Hard memory controllers and PHY up to 2,666 Megabits per
second (Mbps)
High-bandwidth integrated
transceivers
Improved logic integration and hard
IP blocks
Second generation hard processor
system (HPS) with integrated ARM
®
Cortex
™
-A9 MPCore processor
• Tight integration of a dual-core ARM Cortex-A9 MPCore
processor, hard IP, and an FPGA in a single Arria 10 system-
on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data
coherency between the processor and the FPGA fabric
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Summary of Arria 10 Features
3
Advantage
Supporting Feature
Advanced power savings
• Comprehensive set of advanced power saving features
• Power-optimized MultiTrack routing and core architecture
• Up to 40% lower power compared to previous generation of
mid-range FPGAs
• Up to 60% lower power compared to previous generation of
high-end FPGAs
Summary of Arria 10 Features
Table 3: Summary of Features for Arria 10 Devices
Feature
Description
Technology
• TSMC's 20-nm SoC process technology
• Allows operation at a lower V
CC
level of 0.83 V instead of the 0.9 V
standard V
CC
core voltage
• 1.0 mm ball-pitch Fineline BGA packaging
• 0.8 mm ball-pitch Ultra Fineline BGA packaging
• Multiple devices with identical package footprints for seamless migration
between different FPGA densities
• Devices with compatible package footprints allow migration to next
generation high-end Stratix
®
10 devices
• RoHS, leaded
(1)
, and lead-free (Pb-free) options
• Enhanced 8-input ALM with four registers
• Improved multi-track routing architecture to reduce congestion and
improve compilation time
• Hierarchical core clocking architecture
• Fine-grained partial reconfiguration
• M20K—20-Kb memory blocks with hard error correction code (ECC)
• Memory logic array block (MLAB)—640-bit memory
Packaging
High-performance FPGA
fabric
Internal memory blocks
(1)
Contact Altera for availability.
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Summary of Arria 10 Features
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2016.02.11
Feature
Description
Variable-precision • Native support for signal processing precision levels
DSP
from 18 x 19 to 54 x 54
• Native support for 27 x 27 multiplier mode
• 64-bit accumulator and cascade for systolic finite
impulse responses (FIRs)
• Internal coefficient memory banks
• Preadder/subtractor for improved efficiency
• Additional pipeline register to increase performance
and reduce power
• Supports floating point arithmetic:
• Perform multiplication, addition, subtraction,
multiply-add, multiply-subtract, and complex
multiplication.
• Supports multiplication with accumulation
capability, cascade summation, and cascade
subtraction capability.
• Dynamic accumulator reset control.
• Support direct vector dot and complex multiplica‐
tion chaining multiply floating point DSP blocks.
Embedded Hard IP blocks
Memory controller DDR4, DDR3, and DDR3L
PCI Express
®
PCI Express (PCIe
®
) Gen3 (x1, x2, x4, or x8), Gen2 (x1,
x2, x4, or x8) and Gen1 (x1, x2, x4, or x8) hard IP with
complete protocol stack, endpoint, and root port
• 10GBASE-KR/40GBASE-KR4 Forward Error
Correction (FEC)
• PCS hard IPs that support:
10-Gbps Ethernet (10GbE)
PCIe PIPE interface
Interlaken
Gbps Ethernet (GbE)
Common Public Radio Interface (CPRI) with
deterministic latency support
• Gigabit-capable passive optical network (GPON)
with fast lock-time support
• 13.5G JESD204b
• 8B/10B, 64B/66B, 64B/67B encoders and decoders
• Custom mode support for proprietary protocols
•
•
•
•
•
Transceiver I/O
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Summary of Arria 10 Features
5
Feature
Description
Core clock networks
• Up to 800 MHz fabric clocking, depending on the application:
• 667 MHz external memory interface clocking with 2,666 Mbps DDR4
interface
• 800 MHz LVDS interface clocking with 1,600 Mbps LVDS interface
• Global, regional, and peripheral clock networks
• Clock networks that are not used can be gated to reduce dynamic power
Phase-locked loops (PLLs)
• High-resolution fractional synthesis PLLs:
• Precision clock synthesis, clock delay compensation, and zero delay
buffering (ZDB)
• Support integer mode and fractional mode
• Fractional mode support with third-order delta-sigma modulation
• Integer PLLs:
• Adjacent to general purpose I/Os
• Support external memory and LVDS interfaces
FPGA General-purpose I/Os • 1.6 Gbps LVDS—every pair can be configured as receiver or transmitter
(GPIOs)
• On-chip termination (OCT)
• 1.2 V to 3.0 V single-ended LVTTL/LVCMOS interfacing
External Memory Interface
• Hard memory controller— DDR4, DDR3, and DDR3L support
• DDR4—speeds up to 1,333 MHz/2,666 Mbps
• DDR3—speeds up to 1,067 MHz/2,133 Mbps
• Soft memory controller—provides support for RLDRAM 3
(2)
, QDR IV
(2)
,
and QDR II+
(2)
Arria 10 devices support this external memory interface using hard PHY with soft memory controller.
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