LTC1569-6
Linear Phase, DC Accurate,
Low Power, 10th Order Lowpass Filter
FEATURES
s
s
s
s
s
s
s
s
s
s
s
One External R Sets Cutoff Frequency
Root Raised Cosine Response
3mA Supply Current with a Single 3V Supply
Up to 64kHz Cutoff on a Single 3V Supply
10th Order, Linear Phase Filter in an SO-8
DC Accurate, V
OS(MAX)
= 5mV
Low Power Modes
Differential or Single-Ended Inputs
80dB CMRR (DC)
82dB Signal-to-Noise Ratio, V
S
= 5V
Operates from 3V to
±5V
Supplies
tems.
Furthermore, its root raised cosine response offers
the optimum pulse shaping for PAM data communica-
tions.
The filter attenuation is 50dB at 1.5 • f
CUTOFF
, 60dB
at 2 • f
CUTOFF
, and in excess of 80dB at 6 • f
CUTOFF
. DC-
accuracy-sensitive applications benefit from the 5mV
maximum DC offset.
APPLICATIO S
s
s
s
Data Communication Filters for 3V Operation
Linear Phase and Phase Matched Filters for I/Q
Signal Processing
Pin Programmable Cutoff Frequency Lowpass Filters
DESCRIPTIO
®
The LTC1569-6 sampled data filter does not require an
external clock yet its cutoff frequency can be set with a
single external resistor with a typical accuracy of 3.5% or
better.
The external resistor programs an internal oscilla-
tor whose frequency is divided by either 1, 4 or 16 prior to
being applied to the filter network. Pin 5 determines the
divider setting. Thus, up to three cutoff frequencies can be
obtained for each external resistor value. Using various
resistor values and divider settings, the cutoff frequency
can be programmed over a range of six octaves. Alterna-
tively, the cutoff frequency can be set with an external
clock and the clock-to-cutoff frequency ratio is 64:1. The
ratio of the internal sampling rate to the filter cutoff
frequency is 128:1.
The LTC1569-6 is fully tested for a cutoff frequency of
64kHz with a single 3V supply.
The LTC1569-6 features power saving modes and it is
available in an SO-8 surface mount package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC 1569-6 is a 10th order lowpass filter featuring
linear phase and a root raised cosine amplitude response.
The high selectivity of the LTC1569-6 combined with its
linear phase in the passband makes it suitable for filtering
both in data communications and data acquisition sys-
TYPICAL APPLICATIO
Single 3V Supply, 64kHz/16kHz/4kHz Lowpass Filter
V
IN
3V
3.48k
3
2k
1µF
4
V
–
DIV/CLK
5
1/1
1
2
IN
+
IN
–
OUT
V
+
8
7
V
OUT
R
EXT
= 10k
1µF
6
1/16
1/4
3V
GAIN (dB)
3V
LTC1569-6
GND
R
X
EASY TO SET f
CUTOFF
:
f
CUTOFF
=
1, 4 OR 16
64kHz (10k/R
EXT
)
1569-6 TA01
U
U
U
Frequency Response, f
CUTOFF
= 64kHz/16kHz/4kHz
0
–20
–40
–60
–80
100pF
–100
1
10
100
FREQUENCY (kHz)
1000
1569-6
TA01a
1
LTC1569-6
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
IN
+
1
IN
–
2
GND 3
V
–
4
8
7
6
5
OUT
V
+
R
X
DIV/CLK
Total Supply Voltage ................................................ 11V
Power Dissipation .............................................. 500mW
Operating Temperature
LTC1569C ............................................... 0°C to 70°C
LTC1569I ............................................ – 40°C to 85°C
Storage Temperature ............................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1569CS8-6
LTC1569IS8-6
S8 PART
MARKING
15696
1569I6
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 150°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
S
= 3V (V
+
= 3V, V
–
= 0V), f
CUTOFF
= 64kHz, R
LOAD
= 10k unless otherwise specified.
PARAMETER
Filter Gain
CONDITIONS
V
S
= 5V, f
CLK
= 4.096MHz,
f
CUTOFF
= 64kHz, V
IN
= 1.4V
P-P
,
R
EXT
= 10k, Pin 5 Shorted
to Pin 4
f
IN
= 1280Hz = 0.02 • f
CUTOFF
f
IN
= 12.8kHz = 0.2 • f
CUTOFF
f
IN
= 32kHz = 0.5 • f
CUTOFF
f
IN
= 51.2kHz = 0.8 • f
CUTOFF
f
IN
= 64kHz = f
CUTOFF
f
IN
= 97.5kHz = 1.5 • f
CUTOFF
(LTC1569I)
f
IN
= 97.5kHz = 1.5 • f
CUTOFF
(LTC1569C)
f
IN
= 128kHz = 2 • f
CUTOFF
f
IN
= 192kHz = 3 • f
CUTOFF
f
IN
= 312Hz = 0.02 • f
CUTOFF
f
IN
= 3125kHz = 0.2 • f
CUTOFF
f
IN
= 7812kHz = 0.5 • f
CUTOFF
f
IN
= 12.5kHz = 0.8 • f
CUTOFF
f
IN
= 15.625kHz = f
CUTOFF
f
IN
= 23.44kHz = 1.5 • f
CUTOFF
(LTC1569I)
f
IN
= 23.44kHz = 1.5 • f
CUTOFF
(LTC1569C)
f
IN
= 31.25kHz = 2 • f
CUTOFF
(LTC1569I)
f
IN
= 31.25kHz = 2 • f
CUTOFF
(LTC1569C)
f
IN
= 46.88kHz = 3 • f
CUTOFF
f
IN
= 1250Hz = 0.02 • f
CUTOFF
f
IN
= 12.5kHz = 0.2 • f
CUTOFF
f
IN
= 31.25kHz = 0.5 • f
CUTOFF
f
IN
= 50kHz = 0.8 • f
CUTOFF
f
IN
= 62.5kHz = f
CUTOFF
f
IN
= 93.75kHz = 1.5 • f
CUTOFF
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
MIN
–0.05
– 0.25
– 0.65
– 1.3
– 5.3
TYP
0.05
– 0.15
– 0.55
– 1.0
– 3.8
– 60
– 60
– 62
– 71
0.05
– 0.15
– 0.55
– 0.9
– 3.4
– 54
– 54
– 60
– 60
– 66
–11
– 111
82
– 79
162
– 91
62.5kHz
±1%
2.1
MAX
0.15
– 0.05
– 0.4
– 0.7
– 2.4
– 40
– 48
– 50
– 60
0.16
– 0.05
– 0.4
– 0.7
– 3.2
– 48
– 50
– 52
– 55
– 60
–108
85
– 75
168
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Deg
Deg
Deg
Deg
Deg
Deg
V
S
= 2.7V, f
CLK
= 1MHz,
f
CUTOFF
= 15.625kHz,
V
IN
= 1V
P-P
, Pin 6 Shorted
to Pin 4, External Clock
– 0.12
– 0.25
– 0.65
– 1.1
– 3.6
Filter Phase
V
S
= 2.7V, f
CLK
= 4MHz,
f
CUTOFF
= 62.5kHz, Pin 6
Shorted to Pin 4,
External Clock
– 114
79
– 83
156
Filter Cutoff Accuracy
when Self-Clocked
Filter Output DC Swing
(Note 6)
R
EXT
= 10.24k from Pin 6 to Pin 7,
V
S
= 3V, Pin 5 Shorted to Pin 4
V
S
= 3V, Pin 3 = 1.11V
q
1.9
3.9
3.7
8.5
V
S
= 5V, Pin 3 = 2V
q
V
S
=
±5V,
Pin 5 Shorted to Pin 7, R
LOAD
= 20k
2
U
V
P-P
V
P-P
V
P-P
V
P-P
V
P-P
W
U
U
W W
W
LTC1569-6
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
S
= 3V (V
+
= 3V, V
–
= 0V), f
CLK
= 4.096MHz, f
CUTOFF
= 64kHz, R
LOAD
= 10k unless otherwise specified.
PARAMETER
Output DC Offset
(Note 2)
Output DC Offset
Drift
Clock Pin Logic Thresholds
when Clocked Externally
CONDITIONS
R
EXT
= 10k, Pin 5 Shorted to Pin 7
V
S
= 3V
V
S
= 5V
V
S
=
±5V
V
S
= 3V
V
S
= 5V
V
S
=
±5V
Min Logical “1”
Max Logical “0”
Min Logical “1”
Max Logical “0”
Min Logical “1”
Max Logical “0”
V
S
= 3V
q
MIN
TYP
±2
±6
±15
25
25
75
2.7
0.5
4.0
0.5
4.0
0.5
3
3.5
MAX
±5
±12
UNITS
mV
mV
mV
µV/°C
µV/°C
µV/°C
V
V
V
V
V
V
R
EXT
= 10k, Pin 5 Shorted to Pin 7
V
S
= 3V
V
S
= 5V
V
S
=
±5V
Power Supply Current
(Note 3)
f
CLK
= 256kHz (40k from Pin 6 to Pin 7,
Pin 5 Open,
÷
4), f
CUTOFF
= 4kHz
4
5
5
6
7
8
11
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mV
RMS
µV
RMS
dB
V
S
= 5V
q
V
S
= 10V
q
4.5
8
q
f
CLK
= 4.096MHz (10k from Pin 6 to Pin 7,
Pin 5 Shorted to Pin 4,
÷
1), f
CUTOFF
= 64kHz
V
S
= 3V
V
S
= 5V
q
9
13
12
q
V
S
= 10V
Clock Feedthrough
Wideband Noise
THD
Clock-to-Cutoff
Frequency Ratio
Max Clock Frequency
(Note 4)
Min Clock Frequency
(Note 5)
Input Frequency Range
V
S
= 3V
V
S
= 5V
V
S
=
±5V
V
S
= 3V, 5V, T
A
< 85°C
V
S
=
±5V
Aliased Components <–65dB
Pin 5 Open
Noise BW = DC to 2 • f
CUTOFF
f
IN
= 3kHz, 1.5V
P-P
, f
CUTOFF
= 32kHz
17
0.1
95
80
64
5
5
7
1.5
3
0.9 • f
CLK
MHz
MHz
MHz
kHz
kHz
Hz
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
DC offset is measured with respect to Pin 3.
Note 3:
If the internal oscillator is used as the clock source and the divide-
by-4 or divide-by-16 mode is enabled, the supply current is reduced as
much as 40% relative to the divide-by-1 mode.
Note 4:
The maximum clock frequency is arbitrarily defined as the
frequency at which the filter AC response exhibits >1dB of gain peaking.
Note 5:
The minimum clock frequency is arbitrarily defined as the frequecy
at which the filter DC offset changes by more than 5mV.
Note 6:
For more details refer to the Input and Output Voltage Range
paragraph in the Applications Information section.
3
LTC1569-6
TYPICAL PERFOR A CE CHARACTERISTICS
Gain vs Frequency
10
1
–10
GAIN (dB)
GAIN (dB)
–30
–50
–70
–90
2.5
10
100
FREQUENCY (kHz)
THD vs Input Frequency
–60
–65
–70
THD (dB)
–75
–80
–85
–90
V
IN
= 1.5V
P-P
f
CUTOFF
= 32kHz
IN
+
TO OUT
0
5
10
15
20
25
INPUT FREQUENCY (kHz)
30
V
S
= 5V
PIN 3 = 2V
–50
–55
–60
THD (dB)
–65
–70
–75
–80
–85
–90
3V Supply Current
10
9
8
DIV-BY-1
I
SUPPY
(mA)
11
10
I
SUPPY
(mA)
6
5
4
3
2
0.1
EXT CLK
7
6
5
DIV-BY-16
4
3
DIV-BY-4
EXT CLK
I
SUPPY
(mA)
7
DIV-BY-16
DIV-BY-4
1
f
CUTOFF
(kHz)
10
4
U W
100
1569-6 G05
Passband Gain and Group Delay
vs Frequency
40
0
36
–1
32
DELAY (µs)
–2
28
–3
24
1000
1569-6 G01
–4
0.2
20
1
10
FREQUENCY (kHz)
80
1569-6 GO2
THD vs Input Voltage
V
S
= 3V
PIN 3 = 1.11V
V
S
= 5V
PIN 3 = 2V
f
IN
= 3kHz
f
CUTOFF
= 32kHz
IN
+
TO OUT
0
0.5
1.0 1.5 2.0 2.5 3.0
INPUT VOLTAGE (V
P-P
)
3.5
4.0
1569-6 G03
1569-6 G04
5V Supply Current
14
±5V
Supply Current
12
9
DIV-BY-1
8
DIV-BY-1
10
EXT CLK
8
6
DIV-BY-16
DIV-BY-4
4
0.1
1
f
CUTOFF
(kHz)
1569-6 G06
10
100
0.1
1
f
CUTOFF
(kHz)
10
100
1569-6 G07
LTC1569-6
PIN FUNCTIONS
IN
+
/IN
–
(Pins 1, 2):
Signals can be applied to either or
both input pins. The DC gain from IN
+
(Pin 1) to OUT
(Pin 8) is 1.0, and the DC gain from Pin 2 to Pin 8 is –1. The
input range, input resistance and output range are de-
scribed in the Applications Information section. Input
voltages which exceed the power supply voltages should
be avoided. Transients will not cause latchup if the current
into/out of the input pins is limited to 20mA.
GND (Pin 3):
The GND pin is the reference voltage for the
filter and should be externally biased to 2V (1.11V) to
maximize the dynamic range of the filter in applications
using a single 5V (3V) supply. For single supply operation,
the GND pin should be bypassed with a quality 1µF
ceramic capacitor to V
–
(Pin 4). The impedance of the
circuit biasing the GND pin should be less than 2kΩ as the
GND pin generates a small amount of AC and DC current.
For dual supply operation, connect Pin 3 to a high quality
DC ground. A ground plane should be used. A poor ground
will increase DC offset, clock feedthrough, noise and
distortion.
V
–
/V
+
(Pins 4, 7):
For 3V, 5V and
±5V
applications a
quality 1µF ceramic bypass capacitor is required from V
+
(Pin 7) to V
–
(Pin 4) to provide the transient energy for the
internal clock drivers. The bypass should be as close as
possible to the IC. In dual supply applications (Pin 3 is
grounded), an additional 0.1µF bypass from V
+
(Pin 7) to
GND (Pin 3) and V
–
(Pin 4) to GND (Pin 3) is recom-
mended.
The maximum voltage difference between GND (Pin 3) and
V
+
(Pin 7) should not exceed 5.5V.
DIV/CLK (Pin 5):
DIV/CLK serves two functions. When the
internal oscillator is enabled, DIV/CLK can be used to
engage an internal divider. The internal divider is set to 1:1
when DIV/CLK is shorted to V
–
(Pin 4). The internal divider
is set to 4:1 when DIV/CLK is allowed to float (a 100pF
bypass to V
–
is recommended). The internal divider is set
to 16:1 when DIV/CLK is shorted to V
+
(Pin 7). In the
divide-by-4 and divide-by-16 modes the power supply
current is reduced by as much as 40%.
When the internal oscillator is disabled (R
X
shorted
to V
–
) DIV/CLK becomes an input pin for applying an
external clock signal. For proper filter operation, the clock
waveform should be a squarewave with a duty cycle as
close as possible to 50% and CMOS voltages levels (see
Electrical Characteristics section for voltage levels). DIV/
CLK pin voltages which exceed the power supply voltages
should be avoided. Transients will not cause latchup if the
fault current into/out of the DIV/CLK pin is limited to 40mA.
R
X
(Pin 6):
Connecting an external resistor between the R
X
pin and V
+
(Pin 7) enables the internal oscillator. The value
of the resistor determines the frequency of oscillation. The
maximum recommended resistor value is 40k and the
minimum is 3.8k. The internal oscillator is disabled by
shorting the R
X
pin to V
–
(Pin 4). (Please refer to the
Applications Information section.)
OUT (Pin 8):
Filter Output. This pin can drive 10kΩ and/or
40pF loads. For larger capacitive loads, an external 100Ω
series resistor is recommended. The output pin can ex-
ceed the power supply voltages by up to
±2V
without
latchup.
U
U
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5
模拟与混合信号
