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128K x 16

Radiation Hardened

Static RAM MCM – 3.3 V

Features

209A542

Product Description

Other

• Read/Write Cycle Times

≤30

ns (-55 °C to 125°C)

• SMD Number Pending

• Asynchronous Operation

• CMOS or TTL Compatible I/O

• Single 3.3 V ±5% Power Supply

• Low Operating Power

• Packaging Options

• 40-Lead Dual Flat Pack (0.855” x 0.710”)

Radiation

• Fabricated with Bulk CMOS 0.5 µm Process

• Total Dose Hardness through 1x10

rad(Si)

• Neutron Hardness through 1x10

N/cm

• Dynamic and Static Transient Upset Hardness

through 1x10

rad(Si)/s

• Soft Error Rate of < 1x10

-11

Upsets/Bit-Day

• Latchup Free

General Description

The 128K x 16 radiation hardened static

RAM is composed of two 128K x 8 SRAM

memory die assembled in a double-sided

ceramic substrate. Each die is a high

performance 131,072 word x 8-bit static

random access memory with industry-

standard functionality. It is fabricated with

BAE SYSTEMS’ radiation hardened

technology and is designed for use in

systems operating in radiation

environments. The RAM operates over the

full military temperature range and requires

a single 3.3 V ±5% power supply. The RAM

is available with CMOS compatible I/O.

Power consumption is typically less than 40

mW/MHz in operation, and less than 20 mW

in the low power disabled mode. The RAM

read operation is fully asynchronous, with an

associated typical access time of 19

nanoseconds.

BAE SYSTEMS’ enhanced bulk CMOS

technology is radiation hardened through

the use of advanced and proprietary design,

layout, and process hardening techniques.

BAE SYSTEMS • 9300 Wellington Road • Manassas, Virginia 20110-4122

Functional Diagram

Top/Bottom Decoder

A1 - A2

Block Address Decoder

L/R Side/Block

A9 - A16

(((256 x 32) x 2 x 4) x 8 x 2) x 2

Row Address Decoder

Memory Cell Array

16 Bit Word Input/Output

Column Address Decoder

DQ0-DQ15

A4-A8

Signal Definitions

A: 0-16

– Address input pins that select a particular

16-bit word within the memory array.

– Bi-directional data pins that serve as data

outputs during a read operation and as

data inputs during a write operation.

– Negative chip select, when at a low level,

allows normal read or write operation.

When at a high level, S1 forces the SRAM

to a precharge condition, holds the data

output drivers in a high impedance state

and disables the data input buffers only. If

this signal is not used, it must be

connected to GND.

DQ: 0-15

– Negative write enable, when at a low level, activates a

write operation and holds the data output drivers in a

high impedance state. When at a high level, W allows

normal read operation.

– Negative output enable, when at a high level holds the

data output drivers in a high impedance state. When at

a low level, the data output driver state is defined by S1

and W. If this signal is not used it must be connected to

GND.

Truth Table

Inputs

(1),(2)

I/O

Notes:

Power

Mode

1) V

for don’t care (X) inputs = V

or V

Active

Standby

2) When G = high, I/O is high-Z.

3) To dissipate the minimum amount of

standby power when in standby mode:

S1 = V

. All other input levels may float.

Write

Read

Standby

(3)

Low

High

Low

High

Low

Data-In

Data-Out

High-Z

Absolute Maximum Ratings

Applied Conditions

(1)

Minimum

Maximum

Storage Temperature Range (Ambient)

Operating Temperature Range T

CASE

Positive Supply Voltage

Input Voltage

(2)

Output Voltage

(2)

Power Dissipation

(3)

Lead Temperature (Soldering 5 sec)

Electrostatic Discharge Sensitivity

(4)

Notes:

-65°C

-55°C

-0.5 V

+150°C

+125°C

+5.5 V

+ 0.5 V

1.25 W

+230°C

(Class II)

1) Stresses above the absolute maximum rating may cause permanent

damage to the device. Extended operation at the maximum levels may

degrade performance and affect reliability. All voltages are with

reference to the module ground leads.

2) Maximum applied voltage shall not exceed +5.5 V.

3) Guaranteed by design; not tested.

4) Class as defined in MIL-STD-883, Method 3015.

Recommended Operating Conditions

Symbol

Parameters

(1)

Minimum

Maximum

Units

GND

Supply Voltage

Supply Voltage Reference

Case Temperature

Input Logic “Low”

Input Logic “High”

Note:

+3.14

0.0

-55

-0.3

+2.0

+3.46

0.0

+125

+0.8

Volt

Celsius

Volt

1)All voltages referenced to GND.

Power Sequencing

Power shall be applied to the device only in the following

sequences to prevent damage due to excessive currents:

• Power-Up Sequence: GND, V

, Inputs

• Power-Down Sequence: Inputs, V

, GND

DC Electrical Characteristics

Limits

Minimum

Maximum

Test

Symbol

Test Conditions

(1)

Device Type

Units

Supply Current

(Cycling Selected)

Supply Current

(Cycling De-Selected)

Supply Current

(Standby)

Data Retention Current

High Level Output Voltage

Low Level Output Voltage

High Level Input Voltage

Low Level Input Voltage

Input Leakage

Output Leakage

DD1

F = F

MAX

= 1/t

AVAV(min)

S1 = GND

No Output Load

F = F

MAX

= 1/t

AVAV(min)

S1 = V

F = 0 MHz

S1 = V

= 2.5 V

= -4 mA

= -200 µA

= 8 mA

= 200 µA

All

360

DD2

All

6.0

DD3

ILK

OLK

(2)

All

6.0

All

2.0

4.0

- 0.5 V

4.0

0.4

0.05

0.8

-20

µA

0 V

≤

5.5 V

0 V

≤

OUT

≤

5.5 V

By Design/

Verified By

Characterization

By Design/

Verified By

Characterization

All

out

(2)

All

Note:

1) Typical operating conditions:

-55°C

≤

case

≤

+125°C; 3.14 V

≤

3.46 V; unless otherwise specified.

2) Guaranteed by design and verified by periodic characterization.

Output Load Circuit

300

Ω

± 10%

2.8V

50 pF + 10%

Read Cycle AC Timing Characteristics

(1)

Minimum or

Maximum

Minimum

Maximum

Minimum

Maximum

Test

Read Cycle Time

Address Access Time

Chip Select Access Time

Output Enable Access Time

Chip Select to Output Active

Output Enable to Output Active

Output Hold After Address Change

Chip Select to Output Disable

Output Enable to Output Disable

Symbol

AVAV (2)

AVQV

SLQV

GLQV

SLQX

GLQX

AXQX

SHQZ

GHQZ

Device Type

All

Limits

Units

Notes:

1)Test conditions: input switching levels V

= 0.5 V/V

-0.5 V (CMOS), input rise and fall times < 5 ns,

input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output

loading C

= 50 pF. For C

> 50 pF, derate access times by 0.02 ns/pF (typical). -55°C

≤

case

≤

+125°C;

3.14 V

≤

3.46 V; unless otherwise specified.

2) Cycle time per individual die.

Read Cycle Timing Diagram

AVAV

Address

Valid Address

AVQV

SLQV

AXQX

SLQX

SHQZ

GLQV

GLQX

Data

Out

GHQZ

Valid Data

High Impedance

参数对比

与209A542-131相近的元器件有：209A542-135、209A542-145、209A542-144、209A542-133、209A542-143、209A542-147、209A542-134、209A542-137、209A542-141。描述及对比如下：

型号	209A542-131	209A542-135	209A542-145	209A542-144	209A542-133	209A542-143	209A542-147	209A542-134	209A542-137	209A542-141
描述	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40	SRAM Module, 128KX16, 30ns, CMOS, CDFP40, 0.855 X 0.710 INCH, CERAMIC, DFP-40
零件包装代码	DFP	DFP	DFP	DFP	DFP	DFP	DFP	DFP	DFP	DFP
包装说明	DFP,	DFP,	DFP,	DFP,	DFP,	DFP,	DFP,	DFP,	DFP,	DFP,
针数	40	40	40	40	40	40	40	40	40	40
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
最长访问时间	30 ns	30 ns	30 ns	30 ns	30 ns	30 ns	30 ns	30 ns	30 ns	30 ns
JESD-30 代码	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40	R-CDFP-F40
内存密度	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit
内存集成电路类型	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE
内存宽度	16	16	16	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1	1	1	1
端子数量	40	40	40	40	40	40	40	40	40	40
字数	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words
字数代码	128000	128000	128000	128000	128000	128000	128000	128000	128000	128000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
组织	128KX16	128KX16	128KX16	128KX16	128KX16	128KX16	128KX16	128KX16	128KX16	128KX16
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	DFP	DFP	DFP	DFP	DFP	DFP	DFP	DFP	DFP	DFP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大供电电压 (Vsup)	3.46 V	3.46 V	3.46 V	3.46 V	3.46 V	3.46 V	3.46 V	3.46 V	3.46 V	3.46 V
最小供电电压 (Vsup)	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子形式	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Base Number Matches	1	1	1	1	1	1	1	1	1	1
筛选级别	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	-	-	-	MIL-PRF-38535 Class Q	-	MIL-PRF-38535 Class V
总剂量	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	-	-	-	1M Rad(Si) V	-	1M Rad(Si) V