SA-110 Microprocessor
Technical Reference Manual
December 2000
Order Number: 278058-002
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Copyright © Intel Corporation, 2000
*Other brands and names are the property of their respective owners.
SA-110 Microprocessor Technical Reference Manual
Contents
1
Introduction.....................................................................................................................1–1
1.1
1.2
1.3
1.4
Features ............................................................................................................1–1
Applications .......................................................................................................1–2
Document Conventions .....................................................................................1–3
ARM Architecture ..............................................................................................1–3
1.4.1 26-Bit Mode ..........................................................................................1–3
1.4.2 Coprocessors .......................................................................................1–3
1.4.3 Memory Management ..........................................................................1–3
1.4.4 Instruction Cache .................................................................................1–4
1.4.5 Data Cache ..........................................................................................1–4
1.4.6 Write Buffer ..........................................................................................1–4
Block Diagram ...................................................................................................1–4
Functional Diagram ...........................................................................................1–6
1.5
1.6
2
3
Signal Description ..........................................................................................................2–1
ARM Implementation Options ........................................................................................3–1
3.1
3.2
Big and Little Endian .........................................................................................3–1
Exceptions.........................................................................................................3–1
3.2.1 Reset ....................................................................................................3–2
3.2.2 Abort.....................................................................................................3–2
3.2.3 Vector Summary...................................................................................3–3
3.2.4 Exception Priorities...............................................................................3–3
3.2.5 Interrupt Latencies................................................................................3–4
Coprocessors ....................................................................................................3–4
Instruction Timings ............................................................................................4–1
Internal Coprocessor Instructions......................................................................5–1
Registers ...........................................................................................................5–2
5.2.1 Register 0 – ID .....................................................................................5–2
5.2.2 Register 1 – Control .............................................................................5–3
5.2.3 Register 2 – Translation Table Base ....................................................5–4
5.2.4 Register 3 – Domain Access Control ...................................................5–4
5.2.5 Register 4 – RESERVED .....................................................................5–4
5.2.6 Register 5 – Fault Status......................................................................5–4
5.2.7 Register 6 – Fault Address...................................................................5–4
5.2.8 Register 7 – Cache Control Operations ...............................................5–5
5.2.9 Register 8 – TLB Operations................................................................5–5
5.2.10 Registers 9..14 – RESERVED .............................................................5–5
5.2.11 Register 15 – Test, Clock, and Idle Control..........................................5–6
5.2.11.1
Icache LFSR Controls ........................................................5–6
5.2.11.2
Clock Controls....................................................................5–6
3.3
4
5
4.1
5.1
5.2
Instruction Set ................................................................................................................4–1
Configuration ..................................................................................................................5–1
SA-110 Microprocessor Technical Reference Manual
iii
6
Caches and Write Buffer ................................................................................................ 6–1
6.1
Instruction Cache (Icache) ................................................................................ 6–1
6.1.1 Icache Operation .................................................................................. 6–1
6.1.2 Icache Validity ...................................................................................... 6–1
6.1.2.1
Software Icache Flush ....................................................... 6–1
6.1.3 Icache Enable/Disable and Reset ........................................................ 6–1
6.1.3.1
Enabling the Icache ........................................................... 6–2
6.1.3.2
Disabling the Icache........................................................... 6–2
Data Cache (Dcache)....................................................................................... 6–2
6.2.1 Cacheable Bit – C ................................................................................ 6–2
6.2.2 Bufferable Bit – B ................................................................................. 6–2
6.2.3 Dcache Operation ................................................................................ 6–2
6.2.3.1
Cacheable Reads – C=1.................................................... 6–2
6.2.3.2
Noncacheable Reads – C=0.............................................. 6–3
6.2.4 Dcache Validity .................................................................................... 6–3
6.2.4.1
Software Data Cache Flush ............................................... 6–3
6.2.4.2
Doubly-Mapped Space ...................................................... 6–3
6.2.5 Dcache Enable/Disable and Reset ...................................................... 6–3
6.2.5.1
Enabling the Dcache.......................................................... 6–4
6.2.5.2
Disabling the Dcache ......................................................... 6–4
Write Buffer (WB) .............................................................................................. 6–4
6.3.1 Bufferable Bit........................................................................................ 6–4
6.3.2 Write Buffer Operation ......................................................................... 6–4
6.3.2.1
Writes to a Bufferable and Cacheable Location
(B=1, C=1)............................................................................... 6–4
6.3.2.2
Writes to Bufferable and Noncacheable Location
(B=1, C=0)............................................................................... 6–5
6.3.2.3
Unbufferable Writes (B=0) ................................................. 6–5
6.3.3 Enabling the Write Buffer ..................................................................... 6–5
6.3.4 Disabling the Write Buffer .................................................................... 6–5
MMU Registers ................................................................................................. 7–1
MMU Faults and CPU Aborts............................................................................ 7–1
External Aborts.................................................................................................. 7–2
7.3.1 Cacheable Reads (Cache Line Fills).................................................... 7–2
7.3.2 Buffered Writes .................................................................................... 7–2
Interaction of the MMU, Icache, Dcache and Write Buffer ................................ 7–3
SA-110 Operating Modes.................................................................................. 8–1
SA-110 Clocking ............................................................................................... 8–1
8.2.1 Switching to Idle Mode ......................................................................... 8–2
8.2.2 Switching to Sleep Mode...................................................................... 8–2
8.2.3 Core Clock Configuration (CCCFG) ..................................................... 8–2
8.2.4 Memory Clock Configuration (MCCFG) ............................................... 8–2
8.2.5 Tester and Debug Clocks..................................................................... 8–3
Bus Modes ........................................................................................................ 9–1
9.1.1 Standard and Enhanced Mode ............................................................ 9–1
6.2
6.3
7
Memory-Management Unit (MMU)................................................................................. 7–1
7.1
7.2
7.3
7.4
8
8.1
8.2
Clocks ............................................................................................................................ 8–1
9
Bus Interface .................................................................................................................. 9–1
9.1
iv
SA-110 Microprocessor Technical Reference Manual
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
SA-110 Bus Stalls .............................................................................................9–2
Cycle Types.......................................................................................................9–2
Memory Access.................................................................................................9–3
Read/Write ........................................................................................................9–3
Address Pipeline Enable (APE).........................................................................9–3
Memory Access Types ......................................................................................9–3
External Accesses.............................................................................................9–5
9.8.1 Unbuffered Writes/Noncacheable Reads .............................................9–5
Buffered Write ...................................................................................................9–5
Cache Line Fill...................................................................................................9–5
Read-Lock-Write ...............................................................................................9–6
Stalling the Bus .................................................................................................9–7
Summary of Transactions .................................................................................9–7
9.13.1 Read Bursts..........................................................................................9–7
9.13.2 Write Bursts.........................................................................................9–7
9.13.3 Transaction Summary .........................................................................9–8
Overview ......................................................................................................... 10–1
Reset ...............................................................................................................10–2
Pull-Up Resistors............................................................................................. 10–2
nPWRSLP ....................................................................................................... 10–2
Instruction Register ......................................................................................... 10–2
Public Instructions ...........................................................................................10–3
10.6.1 EXTEST (00000) ................................................................................ 10–3
10.6.2 SAMPLE/PRELOAD (00001) ............................................................. 10–3
10.6.3 CLAMP (00100).................................................................................. 10–4
10.6.4 HIGHZ (00101)................................................................................... 10–4
10.6.5 IDCODE (00110) ................................................................................ 10–4
10.6.6 BYPASS (11111)................................................................................ 10–4
Test Data Registers......................................................................................... 10–5
10.7.1 Bypass Register ................................................................................. 10–6
10.7.2 Device Identification (ID) Code Register ............................................ 10–6
10.7.3 Boundary-Scan (BS) Register ............................................................ 10–7
Boundary-Scan Interface Signals.................................................................... 10–8
Absolute Maximum Ratings............................................................................. 11–1
DC Operating Conditions ................................................................................ 11–1
DC Characteristics .......................................................................................... 11–2
Power Supply Voltages and Currents ............................................................. 11–2
Test Conditions ............................................................................................... 12–1
Module Considerations.................................................................................... 12–1
Main Bus Signals............................................................................................. 12–2
SA-110 AC Parameters................................................................................... 12–4
TQFP Pinout.................................................................................................... 13–2
10
Boundary-Scan Test Interface...................................................................................... 10–1
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
11
11.1
11.2
11.3
11.4
12
12.1
12.2
12.3
12.4
13
13.1
DC Parameters............................................................................................................. 11–1
AC Parameters............................................................................................................. 12–1
Package and Pinout ..................................................................................................... 13–1
SA-110 Microprocessor Technical Reference Manual
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