24AA1025/24LC1025/24FC1025
1024K I
2
C
™
Serial EEPROM
Device Selection Table:
Part
Number
24AA1025
24LC1025
24FC1025
†
100
V
CC
Range
1.7-5.5V
2.5-5.5V
1.8-5.5V
Max. Clock
Frequency
400 kHz
†
400 kHz*
1 MHz
‡
Temp.
Ranges
I
I, E
I
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
kHz for V
CC
< 2.5V
*100 kHz for V
CC
< 4.5V, E-temp
‡
400 kHz for V
CC
< 2.5V
Package Type
PDIP
A0
A1
A2*
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Features:
• Low-Power CMOS Technology:
- Read current 450
A,
maximum
- Standby current 5
A,
maximum
• 2-Wire Serial Interface, I
2
C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIJ and SOIC
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Automotive (E): -40C to +125C
SOIJ/SOIC
A0
A1
A2*
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
*A2 must be tied to V
CC
.
Block Diagram
A0 A1
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
Description:
The Microchip Technology Inc. 24AA1025/24LC1025/
24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)
Serial Electrically Erasable PROM, capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
SDA
V
CC
V
SS
Sense AMP
R/W Control
*24XX1025 is used in this document as a generic part number
for the 24AA1025/24LC1025/24FC1025 devices.
2005-2013 Microchip Technology Inc.
DS20001941L-page 1
24AA1025/24LC1025/24FC1025
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
.......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): V
CC
= +2.5V to 5.5V T
A
= -40°C to +125°C
Min.
—
0.7 V
CC
—
0.05 V
CC
Max.
—
—
0.3 V
CC
0.2 V
CC
—
Units
—
V
V
V
V
V
CC
2.5V
V
CC
< 2.5V
V
CC
2.5V
(Note)
Conditions
DC CHARACTERISTICS
Param.
No.
Sym.
—
D1
D2
D3
V
IH
V
IL
V
HYS
Characteristic
A1, A2, SCL, SDA and
WP pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
D4
D5
D6
D7
D8
D9
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CCS
—
—
—
—
—
—
—
0.40
±1
±1
10
450
5
5
V
A
A
pF
A
mA
A
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
SCL, SDA, V
CC
= 5.5V
A1, A2, WP = V
SS
I
CC
Read Operating current
Standby current
Note:
This parameter is periodically sampled and not 100% tested.
DS20001941L-page 2
2005-2013 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A
= -40°C to +125°C
Characteristic
Clock frequency
Min.
—
—
—
—
—
4000
4000
600
600
500
4700
4700
1300
1300
500
—
—
—
—
—
—
—
4000
4000
600
600
250
4700
4700
600
600
250
0
250
250
100
100
100
4000
4000
600
600
250
Max.
100
100
400
400
1000
—
—
—
—
—
—
—
—
—
—
1000
1000
300
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
kHz
Conditions
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
All except 24FC1025
1.8V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
(Note
2)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
AC CHARACTERISTICS
Param.
No.
1
Sym.
F
CLK
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note
1)
ns
5
6
T
F
SDA and SCL fall time
(Note
1)
ns
ns
T
HD
:
STA
Start condition hold time
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
Note 1:
2:
3:
4:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
2005-2013 Microchip Technology Inc.
DS20001941L-page 3
24AA1025/24LC1025/24FC1025
AC CHARACTERISTICS (Continued)
Param.
No.
11
Sym.
T
SU
:
WP
Characteristic
WP setup time
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A
= -40°C to +125°C
Min.
4000
4000
600
600
600
4700
4700
1300
1300
1300
—
—
—
—
—
4700
4700
1300
1300
500
—
—
1,000,000
Max.
—
—
—
—
—
—
—
—
—
—
3500
3500
900
900
400
—
—
—
—
—
50
5
—
Units
ns
Conditions
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
All except 24FC1025
(Note
1
and
Note 3)
—
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
(Note
2)
ns
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
ns
15
16
17
T
SP
T
WC
Note 1:
2:
3:
4:
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
ns
ms
cycles Page mode, 25°C, V
CC
= 5.5V
(Note
4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
2
D3
4
SCL
SDA
IN
7
6
15
3
8
9
10
13
SDA
OUT
(protected)
(unprotected)
14
WP
11
12
DS20001941L-page 4
2005-2013 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
PIN FUNCTION TABLE
PDIP
1
2
3
SOIJ
1
2
3
SOIC
1
2
3
Function
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard-wired to logical 1 state (V
CC
). Operation will
be undefined with this pin left floating or held to logical 0 (V
SS
).
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+1.8 to 5.5V (24FC1025)
V
SS
SDA
SCL
WP
V
CC
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
2.1
A0, A1 Chip Address Inputs
2.3
Serial Data (SDA)
The A0 and A1 inputs are used by the 24XX1025 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k for 100 kHz, 2 kfor
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC
in order for this device to operate.
If left floating or tied to V
SS
, device operation will be
undefined.
2.5
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited, but read operations are
not affected.
2005-2013 Microchip Technology Inc.
DS20001941L-page 5
