3PD9708(E)
8-BIT CMOS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
125 MSPS Update Rate
8-Bit Resolution
Linearity: 1/4 LSB DNL
Linearity: 1/4 LSB INL
Differential Current Outputs
SINAD @ 5 MHz Output: 50 dB
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.10 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead TSSOP
Edge-Triggered Latches
Fast Settling: 35 ns Full-Scale Settling to 0.1%
full-scale output current of 20 mA and > 100 kΏ output
impedance.
Differential current outputs are provided to support
single-ended or differential applications. The current
outputs may be directly tied to an output resistor to
provide two complementary, single-ended voltage
outputs. The output voltage compliance range is 1.25 V.
The 3PD9708(E) contains a 1.1 V on-chip reference and
reference control amplifier, which allows the full-scale
output current to be simply set by a single resistor. The
3PD9708(E) can be driven by a variety of external
reference voltages.
The 3PD9708(E)’s full-scale current can be adjusted over
a 2 mA to 20 mA range without any degradation in
dynamic performance. Thus, the 3PD9708(E) may
operate at reduced power levels or be adjusted over a 20
dB range to provide additional gain ranging capabilities.
The 3PD9708(E) is available in 28-lead TSSOP package.
It is specified for operation over the industrial temperature
range.
APPLICATIONS
Communications
Signal Reconstruction
Instrumentation
Video re-construction
PRODUCT DESCRIPTION
The 3PD9708(E) offers exceptional ac and dc
performance while supporting update rates up to 125
MSPS. The 3PD9708(E)’s flexible single-supply
operating range of +2.7 V to +5.5 V and low power
dissipation are well suited for portable and low power
applications. Its power dissipation can be further reduced
to 45 mW, without a significant degradation in
performance, by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 20 mW.
The 3PD9708(E) is manufactured on an advanced
CMOS process. A segmented current source architecture
is combined with a proprietary switching technique to
reduce spurious components and enhance dynamic
performance. Edge-triggered input latches and a
temperature compensated bandgap reference have been
integrated to provide a complete monolithic DAC solution.
Flexible supply options support +3 V and +5 V CMOS
logic families.
The 3PD9708(E) is a current-output DAC with a nomina
l
PRODUCT HIGHLIGHTS
Manufactured on a CMOS process, the 3PD9708(E)
uses a proprietary switching technique that
enhances dynamic performance well beyond 8- and
10-bit video DACs.
On-chip, edge-triggered input CMOS latches readily
interface to +3 V and +5 V CMOS logic families. The
3PD9708(E) can support update rates up to 125
MSPS.
A flexible single-supply operating range of +2.7 V to
+5.5 V and a wide full-scale current adjustment span
of 2 mA to 20 mA allows the 3PD9708(E) to operate
at reduced power levels (i.e., 45 mW) without any
degradation in dynamic performance.
A temperature compensated, 1.10 V bandgap
reference is included on-chip providing a complete
DAC solution. An external reference may be used.
The current output(s) of the 3PD9708(E) can easily
be configured for various single-ended or differential
applications.
FUNCTIONAL BLOCK DIAGRAM
VERSION : 1.0.2
3PEAKIC Microelectronics Co., Ltd
-1-
3PD9708(E)
8-BIT CMOS
DIGITAL-TO-ANALOG CONVERTER
3PD9708(E)–SPECIFICATIONS
DC SPECIFICATIONS
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless
otherwise noted)
Parameter
RESOLUTION
MONOTONICITY
1
DC ACCURACY
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error(Without Internal Reference)
Gain Error (With Internal Reference)
2
Full-Scale Output Current
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
3
Reference Output Current
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o
4
CCOMP1)
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
5
AVDD
DVDD
Analog Supply Current (I
AVDD
)
6
Digital Supply Current (I
DVDD
)
Supply Current Sleep Mode (I
OUTB
)
6
Power Dissipation (5 V, I
OUTFS
= 20
mA)
7
Power Dissipation (5 V, I
OUTFS
= 20
mA)
7
Power Dissipation (3 V, I
OUTFS
= 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
OPERATING RANGE
Min
Typ
Max
Units
8
Bits
GUARANTEED OVER SPECIFIED TEMPERATURE RANGE
–1
–1/2
–0.025
–10
–10
2
–1.0
± 1/2
± 1/4
+1
+1/2
+0.025
+10
+10
20.0
1.25
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΏ
pF
V
nA
V
M
MHz
ppm of FSR/°
C
ppm of FSR/°
C
ppm of FSR/°
C
ppm/°
C
±2
±1
100
5
1.08
1.1
100
1.12
0.1
1
1.4
0
± 50
± 100
± 50
1.25
1.4
2.7
2.7
5
5
25
3
140
190
45
5.5
5.5
30
6
8.5
175
V
V
mA
mA
µA
mW
mW
–0.4
–0.025
–40
45
+0.4
+0.025
+85
mW
% of FSR/V
% of FSR/V
°
C
NOTES
1. Measured at IOUTA, driving a virtual ground.
2. Nominal full-scale current, I
OUTFS
, is 32 x the I
REF
current.
3. Use an external buffer amplifier to drive any external load.
4. Reference bandwidth is a function of external cap at COMP1 pin.
5. For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to
maintain optimum performance.
6. Measured at f
CLOCK
= 50 MSPS and f
OUT
= 1.0 MHz.
7. Measured as unbuffered voltage output into 50
R
LOAD
at IOUTA and IOUTB, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz. Specifications subject to change without notice.
VERSION : 1.0.2
3PEAKIC Microelectronics Co., Ltd
-2-
3PD9708(E)
8-BIT CMOS
DIGITAL-TO-ANALOG CONVERTER
DYNAMIC SPECIFICATIONS
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Single-Ended
Output, IOUTA, 50 V Doubly Terminated, unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
1
Output Settling Time (tST) (to 0.1%)
Output Propagation Delay (tPD)
Glitch Impulse
1
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
Output Noise (I
OUTFS
= 20 mA)
Output Noise (I
OUTFS
= 2 mA)
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion Ratio
fCLOCK = 10 MSPS; f
OUT
= 1.00 MHz
fCLOCK = 50 MSPS; f
OUT
= 1.00 MHz
fCLOCK = 50 MSPS; f
OUT
= 12.51 MHz
fCLOCK = 100 MSPS; f
OUT
= 5.01 MHz
fCLOCK = 100 MSPS; f
OUT
= 25.01 MHz
Total Harmonic Distortion
fCLOCK = 10 MSPS; f
OUT
= 1.00 MHz
fCLOCK = 50 MSPS; f
OUT
= 1.00 MHz
fCLOCK = 50 MSPS; f
OUT
= 12.51 MHz
fCLOCK = 100 MSPS; f
OUT
= 5.01 MHz
fCLOCK = 100 MSPS; f
OUT
= 25.01 MHz
NOTES
1Measured single ended into 50
Ωload.
Min
100
35
1
5
2.5
2.5
50
30
50
50
48
50
45
-67
-72
-59
-64
-48
Typ
Max
125
Units
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(TMIN
to TMAX, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise
noted)
Parameter
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
Specifications subject to change without notice.
Min
3.5
2.1
–10
–10
5
2
1.5
3.5
Typ
5
3
0
0
Max
Units
V
V
V
V
uA
uA
pF
ns
ns
ns
1.3
0.9
10
10
Figure 1. Timing Diagram
VERSION : 1.0.2
3PEAKIC Microelectronics Co., Ltd
-3-
3PD9708(E)
8-BIT CMOS
DIGITAL-TO-ANALOG CONVERTER
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
to
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
Min
Max
Units
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2–9
10
11–14,25
15
Name
DB7
DB6–DB1
DB0
NC
SLEEP
Description
Most Significant Data Bit (MSB).
Data Bits 1–6.
Least Significant Data Bit (LSB).
No Internal Connection
Power-Down Control Input. Active
High. Contains active pull-down
circuit,
thus
may
be
left
unterminated if not used.
Reference Ground when Internal
1.1 V Reference Used. Connect to
AVDD
to
disable
internal
reference.
Reference Input/Output. Serves as
reference input when internal
reference disabled (i.e., Tie
REFLO to AVDD). Serves as 1.1 V
reference output when internal
reference activated (i.e., Tie
REFLO to ACOM). Requires 0.1
F capacitor to ACOM when
internal reference activated.
Full-Scale Current Output Adjust.
Bandwidth/Noise
Reduction
Node.Add 0.1
F to AVDD for
optimum performance.
Analog Common.
Complementary DAC Current
Output. Full-scale current when all
data bits are 0s.
DAC current Output. Full-scale
current when all data bits are 1s.
Internal Bias Node for Switch
Driver Circuitry. Decouple to
ACOM with 0.1
F capacitor.
Analog Supply Voltage (+2.7 V to
+5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to
+5.5 V).
Clock Input. Data latched on
negtive of clock of 3PD9708and
positive edge of clock of
3PD9708E.
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
COMP1,
COMP2
REFIO, FSADJ
REFLO
Junction
Temperature
Storage
Temperature
Lead
Temperature
(10 sec)
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
6.5
6.5
0.3
6.5
DVDD+ 0.3
DVDD+0.3
AVDD+ 0.3
AVDD+ 0.3
AVDD+ 0.3
0.3
150
V
V
V
V
V
V
V
V
V
V
°
C
°
C
°
C
16
REFLO
17
REFIO
–65
150
300
18
19
20
21
22
23
24
26
27
FS ADJ
COMP1
ACOM
IOUTB
IOUTA
COMP2
AVDD
DCOM
DVDD
*Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum ratings for
extended periods may effect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOIC
C/W
JA
= 71.4°
JC
= 23°C/W
28-Lead TSSOP
C/W
JA
= 97.9°
C/W
JC
= 14.0°
28
CLOCK
PIN CONFIGURATION
ORDERING GUIDE
Model
3PD9708
3PD9708E
Temperature
Range
–40°Cto+85°
C
–40°Cto+85°
C
Package
28-Lead
TSSOP
28-Lead
TSSOP
Package
Option
VERSION : 1.0.2
3PEAKIC Microelectronics Co., Ltd
-4-
3PD9708(E)
8-BIT CMOS
DIGITAL-TO-ANALOG CONVERTER
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or
INL)
Linearity error is defined as the maximum deviation
of the actual analog output from the ideal output,
determined by a straight line drawn from zero to full
scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value,
normalized to full scale, associated with a 1 LSB
change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either
increases or remains constant as the digital input
increases.
Offset Error
The deviation of the output current from the ideal of
zero is called offset error. For I
OUTA
, 0 mA output is
expected whenvcthe inputs are all 0s. For I
OUTB
, 0 mA
output is expected when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output
span. The actual span is determined by the output
when all inputs are set to 1s minus the output when all
inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a
current-output DAC. Operation beyond the maximum
compliance limits may cause either output stage
saturation or breakdown resulting in nonlinear
performance.
Temperature Drift
Temperature drift is specified as the maximum change
from the ambient (+25° value to the value at eith er
C)
TMIN or TMAX. For offset and gain drift, the drift is
reported in ppm of full-scale range (FSR) per degree C.
For reference drift, the drift is reported in ppm per
degree C.
Power Supply Rejection
The maximum change in the full-scale output as the
supplies are varied from nominal to minimum and
maximum specified voltages.
Settling Time
The time required for the output to reach and remain
within a specified error band about its final value,
measured from the start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to
undesired output transients that are quantified by a
glitch impulse. It is specified as the net area of the
glitch in pV-s.
Spurious-Free Dynamic Range
The difference in dB,between the rms amplitude of the
output signal and the peak spurious signal over the
specified bandwidth.
Signal-to-Noise and Distortion (S/N+D, SINAD)
Ratio
S/N+D is the ratio of the rms value of the measured
output
signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but
excluding dc. The value for S/N+D is expressed in
decibels.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels
Figure 2. Basic AC Characterization Test Setup
VERSION : 1.0.2
3PEAKIC Microelectronics Co., Ltd
-5-
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