D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
54F 74F398
54F 74F399 Quad 2-Port Register
May 1995
54F 74F398
54F 74F399
Quad 2-Port Register
General Description
The ’F398 and ’F399 are the logical equivalents of a quad
2-input multiplexer feeding into four edge-triggered flip-
flops A common Select input determines which of the two
4-bit words is accepted The selected data enters the flip-
flops on the rising edge of the clock The ’F399 is the 16-pin
version of the ’F398 with only the Q outputs of the flip-flops
available
Features
Y
Y
Y
Y
Select inputs from two data sources
Fully positive edge-triggered operation
Both true and complement outputs ’F398
Guaranteed 4000V minimum ESD protection
’F399
Commercial
74F398PC
Military
Package
Number
N20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F398DM (Note 2)
74F398SC (Note 1)
54F398FM (Note 2)
54F398LM (Note 2)
74F399PC
54F399DM (Note 2)
74F399SC (Note 1)
74F399SJ (Note 1)
54F399FM (Note 2)
54F399LM (Note 2)
J20A
M20B
W20A
E20A
N20A
J20A
M20B
M20D
W20A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Connection Diagrams
’F398
Pin Assignment
for LCC
Pin Assignment
for DIP SOIC and Flatpak
TL F 9533 – 5
TL F 9533 – 6
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9533
RRD-B30M75 Printed in U S A
Connection Diagrams
(Continued)
’F399
TL F 9533 – 8
TL F 9533– 7
Logic Symbols
’F398
IEEE IEC
’F398
TL F 9533– 2
’F399
TL F 9533 – 1
’F399
TL F 9533– 4
TL F 9533 – 3
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 10
10 10
10 10
50 33 3
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
b
1 mA 20 mA
b
1 mA 20 mA
S
CP
I
0a
–I
0d
I
1a
–I
1d
Q
a
– Q
d
Q
a
– Q
d
Common Select Input
Clock Pulse Input (Active Rising Edge)
Data Inputs from Source 0
Data Inputs from Source 1
Register True Outputs
Register Complementary Outputs (’F398)
2
Functional Description
The ’F398 and ’F399 are high-speed quad 2-port registers
They select four bits of data from either of two sources
(Ports) under control of a common Select input (S) The
selected data is transferred to a 4-bit output register syn-
chronous with the LOW-to-HIGH transition of the Clock in-
put (CP) The 4-bit D-type output register is fully edge-trig-
gered The Data inputs (I
0x
I
1x
) and Select input (S) must be
stable only a setup time prior to and hold time after the
LOW-to-HIGH transition of the Clock input for predictable
operation The ’F398 has both Q and Q outputs
Inputs
S
I
I
h
h
I
0
I
h
X
X
Function Table
Outputs
I
1
X
X
I
h
Q
L
H
L
H
Q
H
L
H
L
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
h
e
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
I
e
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
X
e
Immaterial
’F398 only
Logic Diagram
TL F 9533 – 9
’F398 Only
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
3
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
30 mA to
a
5 0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
b
0 5V to V
CC
Standard Output
b
0 5V to
a
5 5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
’F399
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current (’F398)
Power Supply Current (’F398)
Power Supply Current (’F399)
Power Supply Current (’F399)
b
60
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
20 mA
I
OL
e
20 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V
V
OUT
e
0V
V
O
e
HIGH
V
O
e
LOW
V
O
e
HIGH
V
O
e
LOW
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
25
25
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 6
b
150
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
I
CCL
I
CCH
I
CCL
V
mA
mA
mA
V
mA
mA
mA
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
Max
Max
Max
25
25
22
22
38
38
34
34
4
FPGA/CPLD
