P
RELIMINARY
3.3V 16-Bit Transparent
D-Type Latches
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
24
25
1
48
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
54LVTH162373
Logic Diagram (PositiveLogic)
1/24
1OE/2OE
1LE/2LE
48/25
C1
1D1/2D1
47/36
1D
2/13
1Q1/2Q1
54LVTH162373
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
To Seven Other Channels
Logic Diagram
Memory
F
EATURES
:
• 3.3V low voltage advanced BiCMOS technology (LVT) 16-
bit transparent D-type latches with 3-state outputs
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effect:
- SEL
TH
: No LU > 119 MeV/mg/cm
2
• Package: 48 pin R
AD
-P
AK
® flat package
• Operating temperature range:
- 55 to 125
°
C
• Distributed V
CC
and GND pin configuration minimizes high-
speed switching noise
• Supports mixed-mode signal operation
- 5V input and output voltages with 3.3V V
CC
• Supports unregulated battery operation down to 2.7V
• Supports live insertion
• Bus-hold data inputs eliminate the need for external pullup
resistors
D
ESCRIPTION
:
Maxwell Technologies’ 54LVTH162373 16-bit transparent D-
type latches with 3-state output features a greater than 100
krad (Si) total dose tolerance, depending upon space mission.
The 54LVTH162373 is designed for low voltage (3.3V) V
CC
operation, but with the capability to provide a TTL interface to
a 5V system environment. It is suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working reg-
isters. The 54LVTH162373 can be used as two 8-bit latches or
one 16-bit latch. When the latch-enable (LE) input is low, the
Q output are latched at the levels set up at the data (D) inputs.
When LE is high, the Q outputs follow the D inputs. A buffered
output-enable (OE) input can be used to place the eight out-
puts in either a normal logic state or a high impedance state.
In the high impedance state, the outputs neither load nor drive
the bus lines significantly. The high impedance state and the
increased drive provide the capability to drive bus lines with-
out the need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
1000596
12.19.01 Rev 1
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2001 Maxwell Technologies
All rights reserved.
P
RELIMINARY
3.3V 16-Bit Transparent D-Type
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
1, 24
2, 3, 5, 6, 8, 9, 11, 12
4, 10, 15, 21, 28, 34, 39, 45
7, 31, 42
13, 14, 16, 17, 19, 20, 22, 23
25, 48
26, 27, 29, 30, 32, 31, 32,
33, 35, 36
37, 38, 40, 41, 43, 44, 46, 47
S
YMBOL
1OE-2OE
1Q1-1Q8
GND
V
CC
2Q1-2Q8
2LE-1LE
2D8-2D1
1D8-1D1
Outputs
Ground
Power Supply
Outputs
Latch Enable
Inputs
Inputs
54LVTH162373
D
ESCRIPTION
Output Enable
T
ABLE
2. 54LVTH162373 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Supply voltage range
Input voltage range
1
Voltage range applied to any output in the high state or power-off
state
1
Current into any output in the low state
Current into any output in the high state
2
Input clamp current (V
I
< 0)
Output clamp current (V
O
< O)
Maximum power dissipation at TA = 55
°
C
3
Storage temperature range
S
YMBOL
V
CC
V
I
V
O
I
O
I
O
I
IK
I
OK
P
D
T
S
M
IN
-0.5
-0.5
-0.5
--
--
--
--
--
-65
M
AX
4.6
7
7
30
30
-50
-50
0.85
150
U
NIT
V
V
V
mA
mA
mA
mA
mW
°
C
Memory
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V
O
> V
CC
.
3. The maximum package power dissipation is calculated using a junction temperature of 150
°
C and a board trace length of 750
mils.
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC(OL)
I
CC(OH)
I
CC(OD)
V
ARIATION
±10% of specified value in Table 5
±10% of specified value in Table 5
±10% of specified value in Table 5
1000596
12.19.01 Rev 1
All data sheets are subject to change without notice
2
©2001 Maxwell Technologies
All rights reserved.
P
RELIMINARY
3.3V 16-Bit Transparent D-Type
54LVTH162373
S
YMBOL
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
T
A
M
IN
2.7
2
--
--
--
--
--
-55
M
AX
3.6
--
0.8
5.5
-12
12
10
125
U
NIT
V
V
V
V
mA
mA
ns/V
°
C
T
ABLE
4. 54LVTH162373 R
ECOMMENDED
O
PERATING
C
ONDITIONS 1
P
ARAMETER
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate (outputs enabled)
Operating temperature
∆
t/
∆
v
1. Unused control inputs must be held high or low to prevent them from floating.
T
ABLE
5. 54LVTH162373 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V ±10%, T
A
= -55 to 125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Clamp Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Current
S
YMBOL
V
IK
V
OH
V
OL
I
I
V
CC
= 2.7
V
CC
= 3V
V
CC
= 3V
V
CC
= 0 or 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
Hold Current
Output Disabled Leakage
Current - High
Output Disabled Leakage
Current - Low
Power Up Current
Power Down Current
I
I(HOLD)
V
CC
= 3V
I
OZH
I
OZL
I
OZPU2
I
OZPD2
V
CC
= 3.6V, V
O
= 3V
V
CC
= 3.6V, V
O
= 0.5V
V
CC
= 0 to 1.5V, V
O
= 0.5V to 3V, OE = don’t care
V
CC
= 1.5V to 0, V
O
= 0.5V to 3V, OE = don’t care
T
EST
C
ONDITIONS
I
I
= -18mA
I
OH
= -12 mA
I
OL
= 12 mA
VI = 5.5V
V
I
= V
CC
or GND
V
I
= V
CC
V
I
= 0
V
I
= 0.8V
V
I
= 2V
Control
inputs
Data
Inputs
Data
Inputs
M
IN
--
2
--
--
--
--
--
75
-75
--
--
--
--
M
AX
-1.2
--
0.8
10
±1
1
-5
--
--
5
-5
±100
±100
µA
µA
µA
µA
µA
U
NIT
V
V
V
µA
Memory
1000596
12.19.01 Rev 1
All data sheets are subject to change without notice
3
©2001 Maxwell Technologies
All rights reserved.
P
RELIMINARY
3.3V 16-Bit Transparent D-Type
54LVTH162373
M
IN
Outputs
high
Outputs
low
Outputs
disabled
--
--
--
--
--
--
M
AX
0.19
5
0.19
0.2
8
15
mA
pF
pF
U
NIT
mA
T
ABLE
5. 54LVTH162373 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V ±10%, T
A
= -55 to 125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Supply Current
S
YMBOL
I
CC
V
CC
= 3.6V
I
O
= 0
V
I
= V
CC
or GND
T
EST
C
ONDITIONS
Delta Supply Current
Input Capacitance
Input Output Capacitance
∆
I
CC 1
V
CC
= 3V to 3.6V, One input at V
CC
-0.6V, Other inputs
at V
CC
or GND
C
I2
C
O2
V
I
= 3V or 0
V
O
= 3V or 0
1. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
2. Guaranteed by design.
Memory
T
ABLE
6. 54LVTH162373 AC E
LECTRICAL
C
HARACTERISTICS
(VCC = 3.3V ±10%, T
A
= -55 to 125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Pulse duration, LE high
Setup time, data before LEØ
Hold time, data after LEØ
Propagation Delay Time
D to Q
Propagation Delay Time
LE to Q
Output Enable Time
OE to Q
Output Disable Time
OE to Q
S
YMBOL
t
W
t
SU
t
H
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
V
CC
= 3.3V ± 0.3V
M
IN
3.3
1.5
1.8
1.3
1.4
2.1
2.1
1.3
1.3
2.0
1.0
M
AX
--
--
--
5.2
4.9
6.0
5.2
8.0
5.5
6.8
7.6
M
IN
3.0
0.6
2
--
--
--
--
--
--
--
--
V
CC
= 2.7V
M
AX
--
--
--
6.0
5.0
6.5
4.9
7.4
6.2
6.9
6.7
ns
ns
ns
ns
ns
ns
ns
U
NIT
1000596
12.19.01 Rev 1
All data sheets are subject to change without notice
4
©2001 Maxwell Technologies
All rights reserved.
P
RELIMINARY
3.3V 16-Bit Transparent D-Type
fp
54LVTH162373
T
ABLE
7. F
UNCTION TABLE
(
EACH
8-
BIT SECTION
)
INPUTS
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q
0
Z
F
IGURE
1. L
OAD
C
IRCUIT
Memory
Figure Note:
1. C
L
includes probe and jig capacitance.
P
ARAMETER
M
EASUREMENT
I
NFORMATION
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
OPEN
6V
GND
F
IGURE
2. P
ULSE
D
URATION
1000596
12.19.01 Rev 1
All data sheets are subject to change without notice
5
©2001 Maxwell Technologies
All rights reserved.
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