DATASHEET
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
Description
The ICS581-01/02 are glitch free, Phase Locked Loop
(PLL) based clock multiplexers (mux) with zero delay from
input to output. They each have four low skew outputs
which can be configured as a single output, three outputs,
or four outputs. The ICS581-01 allows user control over the
mux switching, while the ICS581-02 has automatic
switching between the two clock inputs.
The ICS581-01 and -02 are members of IDT’s
ClockBlocks
TM
family of clock generation, synchronization,
and distribution devices. For a non-PLL based clock mux,
see the ICS580-01.
ICS581-01/02
Features
•
•
•
•
•
•
•
•
•
•
•
16-pin TSSOP package
RoHS compliant packaging available
No short pulses or glitches on output
Operates from 6 to 200 MHz
Low skew outputs
User controlled (-01) or automatic, timed mux switch (-02)
Ideal for systems with back-up or redundant clocks
Zero delay (input to output)
50% output duty cycle allows duty cycle correction
SpreadSmart
TM
technology works with spread spectrum
parts
Industrial temperature of ICS581-02 available
Block Diagram
ICS581-01
INA
1
CLK1
INB
SELA
FBIN
0
CLK2
PLL
Output
Divide
CLK3
VDD
2
CLK4
S1:0
2
GND
2
OE0
OE1
ICS581-02
DIV
VDD
2
IN
/48
/3
1
0
1
0
Transition
Detector
INA
INB
CLK1
CLK2
PLL
FBIN
Output
Divide
CLK3
CLK4
S1:0
2
GND
2
OE0
OE1
IDT™ / ICS™
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
1
ICS581-01/02
REV J 120908
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
Pin Assignment
S0
S1
VDD
INA
INB
G ND
FBIN
OE0
1
2
ICS581-01
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SELA
VDD
CLK1
CLK2
CLK3
CLK4
GND
OE1
S0
S1
VDD
INA
INB
G ND
FBIN
OE0
1
2
ICS581-02
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIV
VDD
CLK1
CLK2
CLK3
CLK4
GND
OE1
16 pin 4.40 m il body (0.65 m m pitch) TSSO P
16 pin 4.40 m il body (0.65 m m pitch) TSSO P
Clock Decoding
SELA
0
1
ICS581-01 only
CLK1-4
INB
INA
Timeout Selection
DIV
0
1
ICS581-02 only
Nominal Timeout
3x period of INB
48x period of INB
Tri-State and Power Down
OE1
0
0
1
1
OE0
0
1
0
1
CLK1
Z
On
Z
On
CLK2-4
Z
Z
On
On
PLL
Off
On
On
On
Frequency Range Select
S1
0
0
1
1
S0
0
1
0
1
Input Range (MHz)
50 - 150
19 - 75
6 - 19
150 - 200
ICS581-01/02
Note:
Z indicates that the output is in a high
impedance state
ICS581-01/02
IDT™ / ICS™
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
2
ICS581-01/02
REV J 120908
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 (-01)
16 (-02)
Pin
Name
S0
S1
VDD
INA
INB
GND
FBIN
OE0
OE1
GND
CLK4
CLK3
CLK2
CLK1
VDD
SELA
DIV
Pin
Type
Input
Input
Power
Input
Input
Power
Input
Input
Input
Power
Output
Output
Output
Output
Power
Input
Input
Pin Description
Select 0 for frequency range. See table. Internal pull-up.
Select 1 for frequency range. See table. Internal pull-up.
Power Supply. Connect to +3.3 V or +5 V.
Input Clock A.
Input Clock B.
Connect to ground.
Feedback input. Connect to a clock output.
Output enable 0. See table. Internal pull-up.
Output enable 1. See table. Internal pull-up.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Power Supply. Connect to +3.3 V or +5 V.
Mux select. Selects INA when high. Internal pull-up.
Timeout select. See table. Internal pull-up.
Device Operation
The ICS581-01 and ICS581-02 are very similar. Following is
a description of the operation of the ICS581-01 and the
differences of the ICS581-02.
The ICS581-01 is a PLL-based, zero delay, clock
multiplexer. The device consists of an input multiplexer
controlled by SELA that selects between two clock inputs.
The output of the mux drives the reference input of a phase
locked loop. The other input to the PLL comes from a
feedback input pin called FBIN. The output of the PLL drives
four low skew outputs. These chip outputs are therefore
buffered versions of the selected input clock with zero delay
and 50/50 duty cycle.
For correct operation, one of the clock outputs must be
connected to FBIN. In this datasheet, CLK4 is shown as the
feedback, but any one of the four clock outputs can be used.
If output termination resistors are used, the feedback should
be connected before the resistor. It is a property of the PLL
used on this chip that it will align rising edges on FBIN and
either INA or INB (depending on SELA). Since FBIN is
connected to a clock output, this means that the outputs
appear to align with the input with zero delay.
When the input select (SELA) is changed, the output clock
will change frequency and/or phase until it lines up with the
new input clock. This occurs in a smooth, gradual manner
without any short pulses or glitches and will typically take a
few tens of microseconds.
The part must be configured to operate in the correct
frequency range. The table on page two gives the
recommended range.
The four low skew outputs are controlled by two output
enable pins that allow either one, three, or four simultaneous
outputs. If both OE pins are low, the PLL is powered down.
Note that the clock driving the FBIN pin must not be
tri-stated unless the PLL is powered down. Otherwise the
IDT™ / ICS™
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
3
ICS581-01/02
REV J 120908
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
PLL will run in an open loop.
The ICS581-02 is identical to the ICS581-01 except for the
switching of the input mux. On the ICS581-02, the switching
is automatically controlled by a transition detector. The
transition detector monitors the clock on INA. If this clock
stops, the output of the detector, NO_INA goes high, which
then selects clock input INB to the mux. The definition of the
clock stopping is determined by a timeout selected by input
DIV. If DIV is low, NO_INA will go high after no transitions
have occurred on INA for nominally three cycles of the clock
on INB. If DIV is high, the timeout is nominally 48 cycles of
INB. When INA restarts, the mux immediately switches back
to the INA selection with no timeout.
Input Clock Frequency
The ICS581-01 and ICS581-02 are designed to switch
between two clocks of the same frequency. They will also
operate with different frequencies on each of the two input
clocks. If the two input frequencies require different input
ranges (see table on page two), then the highest range
should be permanently selected. When the selected input
clock is outside this range, jitter and input skew
specifications may not be met. Consult IDT for more
information.
Application Example
A typical application for the ICS581-02 is to provide a backup clock for a system. The backup reliable clock would
be connected to INB while the main clock would be connected to INA. If the main clock failed, the ICS581-02 would
automatically be switched to the backup clock. The following example shows the connection for this.
VDD
S0
S1
0.01 F
DIV
VDD
CLK1
33
0.01 F
VDD
INA
INB
GND
FBIN
OE0
MAIN
BACKUP
CLK2
33
CLK3
33
CLK4
33
GND
OE1
In this example, the clocks are 155 MHz and so the frequency range is address 11. Both S0 and S1 are left
unconnected, causing the on-chip pull-ups to produce the required high inputs. The same is true for OE0, OE1, and
DIV. In this example, CLK4 is used as the feedback. Note that the feedback path is before the series resistor.
IDT™ / ICS™
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
4
ICS581-01/02
REV J 120908
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
External Components
The ICS581-01 and ICS581-02 require two 0.01µF capacitors between VDD and GND, one on each side of the
chip. These must be close to the chip to minimize lead inductance. Series termination resistors of 33Ω should be
used on the outputs, should also be close to the chip, and the feedback path should be a direct connection from a
clock output to a FBIN pin, routed directly under the chip to minimize trace length. This should be connected before
the series termination resistor.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS581-01/02. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (ICS581-01, ICS581-02)
Ambient Operating Temperature (ICS581-01I, ICS581-02I)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS581-01, ICS581-02)
Ambient Operating Temperature (ICS581-01I, ICS581-02I)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.0
Typ.
Max.
+70
+85
+5.5
Units
°
C
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD
IDD
V
IH
V
IL
V
IH
V
IL
Conditions
100 MHz, no load
Non-clock inputs
Non-clock inputs
INA, INB, FBIN
INA, INB, FBIN
Min.
3.0
Typ.
26
Max.
5.5
Units
V
mA
V
2
0.8
(VDD/2)+1
VDD/2
VDD/2
(VDD/2)-1
V
V
V
IDT™ / ICS™
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
5
ICS581-01/02
REV J 120908
