Features
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Low-power Operation Including Special STOP Mode
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Frequency: 16.78 MHz at 5V ± 10% Supply and 20.97 MHz at 5V ± 5%, Software
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Programmable
Technology: 1
µ
High-density Complementary Metal-Oxide Semiconductor (HCMOS),
Static Design
Package: 132-pin Ceramic Leaded Chip Carrier (CERQUAD) and 132-pin Ceramic Pin
Grid Array (PGA)
Modular Architecture in a Single Chip
CPU: 32-bit 6800 Family (Upward Object-code Compatible With The 68010)
New Instructions For Controller Applications
Intelligent 16-bit Timer
– 16 Independent, Programmable Channels
– Any Channel Can Perform Any Time Function (for Example Input Capture, Output
Compare, Pulse Width Modulation, etc.)
– Two timer Count Registers with 2-bit Programmable Prescalers
– Selectable Channel Priority Levels
– Reduced CPU Intervention
– RISC like CPU Within the TPU
Two Serial I/O Subsystems
– Enhanced 68HC11-type Serial Communications Interface (SCI) Universal
Asynchronous Receiver Transmitter (UART) with Parity
– Enhanced 68HC11-type Serial Peripheral Interface With I/O RAM Queue (QSPI)
On-chip Memory: 2-Kbytes Standby RAM
On-chip, Programmable, Chip-select Logic
– Up to 12 Signals for Memory and Peripheral Interface with I/O Select
System Failure Protection
– 68HC11-type Computer Operating Properly (COP) Watchdog Timer
– 68HC11-type Periodic Interrupt Timer
– 68000 Family Spurious Interrupt, Halt, and Bus Time-out Monitors
Up to 48 Discrete I/O Pins
High-
performance
32-bit Integrated
Microcontroller
TS68332
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Description
The TS68332 is a 32-bit microcontroller, combining high-performance data manipula-
tion capabilities with powerful peripheral subsystems. The TS68332 is the first
member of the 68300 family of modular embedded controllers featuring fully static,
high-speed complementary metal-oxide semiconductor technology. Based on the
powerful TS68020, the CPU32 instruction processing module provides enhanced sys-
tem performance and utilizes the extensive software base of the 68000 family.
Rev. 2118A–HIREL–03/02
1
Screening/Quality
This product is manufactured in full compliance with:
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MIL-STD-883 (class B)
DSCC 5962-91501
Or according to Atmel-Grenoble standard
R suffix
PGA 132
Ceramic Pin Grid Array
A suffix
CERQUAD 132
Ceramic Leaded Chip Carrier
Introduction
Figure 1 is a block diagram of the TS68332 showing the major components. The pin
descriptions are provided in Table 1. The TS68332 contains intelligent peripheral mod-
ules such as the Time Processor Unit (TPU), which provides 16 microcoded channels
for performing time-related activities from simple input capture or output compare to
complicated motor control or pulse width modulation. High-speed serial communications
are provided by the Queued Serial Module (QSM) with synchronous and asynchronous
protocols available. 2-Kbytes of fully static standby RAM allow fast two-cycle access for
system and data stacks and variable storage with provision for battery back-up. There is
a System Integration Module (SIM) which includes twelve chip selects to enhance sys-
tem integration for fast external memory or peripheral access. The powerful 32-bit CPU
(CPU 32) is based on the industry-standard TS68020. These modules are connected on
chip via the Intermodule Bus (IMB) and provide reduced system part count, size, cost of
implementation and increased reliability.
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TS68332
2118A–HIREL–03/02
TS68332
Figure 1.
Block Diagram of TS68332
VSTBY
CHIP
SELECTS
TPUCH[15:0]
T2CLK
TPUCH[15:0]
T2CLK
TPU
2 KBYTES
RAM
FC2
FC1
FC0
ADDR[23:19]
CONTROL
PORT C
BR
BG
BGACK
CS[10:0]
CSBOOT
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
ADDR[23:0]
SIZ1
SIZ0
EBI
DS
AS
RMC
AVEC
DSACK1
DSACK0
ADDR[18:0]
PE7/SIZ1
PE6/SIZ0
PE5/DS
PE4/AS
PE3/RMC
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
IMB
RXD
PQS7/TXD
PQS6/PCS3
QS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
TXD
PCS3
PCS2
PCS1
PCS0/SS
SCK
MOSI
MISO
QSM
CPU 32
PORT QS
CONTROL
DATA[15:0]
CONTROL
PORT E
DATA[15:0]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
XFC
VDDSYN
TSC
CONTROL
FREEZE/QUOT
IRQ[7:1]
CONTROL
PORT F
MODCLK
CLOCK
BKPT
IFETCH
IPIPE
DSI
DSO
DSCLK
FREEZE
TSC
CONTROL
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
TEST
QUOT
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2118A–HIREL–03/02
Signal Description
Table 1.
Signal Index
Signal Name
Address Bus
Data Bus
Data Bus Function Codes
Boot Chip Select
Chip Selects
Bus Request
Bus Grant
Bus Grant Acknowledge
Data and Size
Acknowledgement
Autovector
Read-Modify-Write Cycle
Address Strobe
Data Strobe
Size
Read/Write
Interrupt Request Level
Reset
Halt
Bus Error
System Clockout
Crystal Oscillator
External Filter Capacitor
Clock Mode Select
Instruction Fetch
Instruction Pipe
Breakpoint
Freeze
Quotient Out
Test Mode Enable
Three-State Control
Figure 1 illustrates the functional signal groups and Table 1 lists the signals and their
function.
Mnemonic
A23 - A0
D15 - D0
FC2 - FC0
CSBOOT
CS10 - CSO
BR
BG
BGACK
DSACK1,
DSACK0
AVEC
RMC
AS
DS
SIZ1 - SIZ0
R/W
IRQ7 - IRQ0
RESET
HALT
BERR
CLKOUT
EXTAL,
XTAL
XFC
MODCK
IFETCH
IPIPE
BKPT
FREEZE
QUOT
TSTME
TSC
Function
24-bit address bus
16-bit data bus used to transfer byte or word data per bus cycle
Identify the processor state and the address space of the current bus cycle
Chip-select boot stat up ROM containing user’s reset vector and initialization
program
Enables peripherals at programmed addresses
Indicates that an external device requires bus mastership
Indicates that current bus cycle is complete and the TS68332 has relinquished the
bus
Indicates that an external device has assumed bus mastership
Provides asynchronous data transfers and dynamic bus sizing
Requests an automatic vector during an interrupt acknowledge cycle
Identifies the bus cycle as part of an indivisible read-modify-write cycle
Indicates that a valid address is on the address bus
During a read cycle, DS indicates that an external device should place valid data on
the data bus. During a write cycle, DS indicates that valid data is on the data bus.
Indicates the number of bytes remaining to be transferred for this cycle
Indicates the direction of data transfer on the bus
Provides an interrupt priority level to the CPU
System reset
Suspend external bus activity
Indicates that an erroneous bus operation is being attempted
Internal system clock
Connection for an external crystal to the internal oscillator circuit
Connection pin for an external capacitor to filter the circuit of the phase-locked loop
Selects the source of the internal system clock
Indicates when the CPU is performing an instruction word pre-fetch and when the
instruction pipeline has been flushed
Used to track movement of words through the instruction pipeline
Signals a hardware breakpoint to the CPU
Indicates that the CPU has acknowledged a breakpoint
Serial I/O and clock for background debug mode
Hardware enable for test mode
Places all output drivers in a high-impedance state
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TS68332
2118A–HIREL–03/02
TS68332
Table 1.
Signal Index (Continued)
Signal Name
Development Serial In, Out,
Clock
TPU Channels
TPU Clock In
SCI Receive Data
SCI Transmit Data
Peripheral Chip Select
Slave Select
QSPI Serial Clock
Master-in Slave-out
Master-out Slave-in
Standby RAM
Synchronizer Power
System Power Supply and
Return
Mnemonic
DSI, DSO,
DSCLK
TP15 - TP0
T2CLK
RXD
TXD
PCS3 - PCS0
SS
SCK
MISO
MOSI
V
STBY
V
DDSYN
V
DD
, V
SS
Function
Serial I/O and clock for background debug mode
TPU channel input/output Serial I/O and clock for background debug mode
External clock source to the TPU
Serial input to the SCI
Serial output from the SCI
QSPI peripheral chip selects
Places the QSPI in slave mode
Furnishes the clock from the QSPI in master mode or to the QSPI in slave mode
Furnishes serial input to the QSPI in master mode, and serial output from the QSPI in
slave mode
Furnishes serial output from the QSPI in master mode, and serial input to the QSPI in
slave mode
Power supply for RAM
Power supply to VCO
Power supply and return to the MCU
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2118A–HIREL–03/02
PCB设计
