S E M I C O N D U C T O R
HS-1840ARH
Rad-Hard 16 Channel CMOS Analog
Multiplexer with High-Z Analog Input Protection
Description
The HS-1840ARH is a radiation hardened, monolithic 16
channel multiplexer constructed with the Harris Rad-Hard
Silicon Gate, bonded wafer, Dielectric Isolation process. It is
designed to provide a high input impedance to the analog
source if device power fails (open), or the analog signal volt-
age inadvertently exceeds the supply by up to
±35V,
regard-
less of whether the device is powered on or off. Excellent for
use in redundant applications, since the secondary device
can be operated in a standby unpowered mode affording no
additional power drain. More significantly, a very high imped-
ance exists between the active and inactive devices prevent-
ing any interaction. One of sixteen channel selection is
controlled by a 4-bit binary address plus an Enable-Inhibit
input which conveniently controls the ON/OFF operation of
several multiplexers in a system. All inputs have electrostatic
discharge protection.
The HS-1840ARH is processed and screened in full
compliance with MIL-PRF-38535 and QML standards. The
device is available in a 28 lead SBDIP and a 28 lead
Ceramic Flatpack.
Detailed Electrical Specifications are contained in DSCC
SMD Number 5962-95630.
July 1997
Description
• Pin-to-Pin for Harris’ HS-1840RH and HS-1840/883S
• MIL-PRF-38535 Screened to DSCC SMD 5962F95630
• Improved Radiation Performance
- Gamma Dose (γ) 3x 10
5
RAD(Si)
• Improved r
DS(ON)
Linearity
• Improved Access Time 1.5µs (Max) Over Temp and Post
Rad
• High Analog Input Impedance 500MΩ During Power
Loss (Open)
•
±35V
Input Over Voltage Protection (Power On or Off)
• Dielectrically Isolated Device Islands
• Excellent in Hi-Rel Redundant Systems
• Break-Before-Make Switching
• No Latch-Up
Ordering Information
PART
TEMP.
NUMBER
CLASS RANGE (
o
C)
5962F9563002VXC
V
-55 to 125
5962F9563002QXC
Q
-55 to 125
HS1-1840ARH/Proto
-55 to 125
HS1-1840ARH/Sample
25
5962F9563002VYC
V
-55 to 125
5962F9563002QYC
HS9-1840ARH/Proto
HS9-1840ARH/Sample
Q
-55 to 125
-55 to 125
25
PACKAGE
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld Ceramic
Flatpack
28 Ld Ceramic
Flatpack
28 Ld Ceramic
Flatpack
28 Ld Ceramic
Flatpack
PKG.
NO.
D28.6
D28.6
D28.6
D28.6
K28.A
K28.A
K28.A
K28.A
Pinouts
HS1-1840RH (SBDIP) CASE OUTLINE CDIP2-T28,
COMPLIANT TO MIL-STD-1835 PACKAGE
TOP VIEW
+V
S
1
NC 2
NC 3
IN 16 4
IN 15 5
IN 14 6
IN 13 7
IN 12 8
IN 11 9
IN 10 10
IN 9 11
GND 12
(+5V
S
) V
REF
13
ADDR A3 14
28 OUT
27 -V
S
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
HS9-1840RH (CERAMIC FLATPACK) OUTLINE CDFP3-F28,
COMPLIANT TO MIL-STD-1835 PACKAGE
TOP VIEW
+V
S
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5V
S
) V
REF
ADDR A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
-V
S
IN 8
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
ENABLE
ADDR A0
ADDR A1
ADDR A2
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1997
File Number
4355
1
HS-1840ARH
Functional Diagram
A0
1
P
IN 1
A1
DIGITAL
ADDRESS
A2
OUT
A3
16
EN
P
IN 16
ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER
DECODERS
MULTIPLEX
SWITCHES
TRUTH TABLE
A3
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
A2
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A1
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A0
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
EN
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
“ON” CHANNEL
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
HS-1840ARH
Burn-In/Life Test Circuits
R
+V
S
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
-V
S
+V
S
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
-V
S
R
F5
F1
F2
F3
GND
F4
GND
V
R
R
NOTES:
V
S
+ = +15.5V
±0.5V,
V
S
- = -15.5V
±0.5V.
R = 1kΩ
±5%.
C
1
= C
2
= 0.01µF
±10%,
1 each per socket, minimum.
D
1
= D
2
= 1N4002, 1 each per board, minimum.
Input Signals: square wave, 50% duty cycle, 0V to 15V peak
±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
NOTES:
R = 1kΩ
±5%,
1
/
4
W.
C
1
= C
2
= 0.01µF minimum, 1 each per socket, minimum.
V
S
+ = 15.5V
±0.5V,
V
S
- = -15.5V
±0.5V,
V
R
= 15.5
±0.5V.
FIGURE 2. STATIC BURN-IN TEST CIRCUIT
Irradiation Circuit
HS-1840ARH
+15V
NC
NC
+1V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+5V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-15V
1kΩ
NOTE: All irradiation testing is performed in the 28 lead CERDIP package.
3
HS-1840ARH
Die Characteristics
DIE DIMENSIONS:
(2820µm x 4080µm x 483µm
±
25.4µm)
111 x 161 x 19mils
±1mil
METALLIZATION:
Type: Al Si Cu
Thickness: 16.0k
Å
±
2k
Å
SUBSTRATE POTENTIAL:
Unbiased (DI)
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Nitride (Si
3
N
4
) over Silox (S
i
O
2
)
Nitride Thickness: 4.0k
Å
±
0.5k
Å
Silox Thickness: 12.0k
Å
±
1.3k
Å
WORST CASE CURRENT DENSITY:
Modified SEM
TRANSISTOR COUNT:
407
PROCESS:
Radiation Hardened Silicon Gate,
Bonded Wafer, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH
IN7
IN6
IN5
IN4
IN3
IN2
IN8
ENABLE
IN1
A0
-V
A1
OUT
A2
+V
A3
V
REF
IN16
GND
IN15
IN14
IN13
IN12
IN11
4
IN10
IN9
HS-1840ARH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
-D-
BASE
METAL
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D28.6
MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)
28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
SYMBOL
A
b
b1
b2
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.500
MAX
0.232
0.026
0.023
0.065
0.045
0.018
0.015
1.490
0.610
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
12.70
MAX
5.92
0.66
0.58
1.65
1.14
0.46
0.38
37.85
15.49
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 5/18/94
E
M
-B-
bbb S C A - B S
BASE
PLANE
SEATING
PLANE
S1
b2
b
A A
D
S2
-C-
Q
A
L
D S
b3
c
c1
e
A
e
e
A/2
c
D
E
e
eA
eA/2
L
Q
S1
S2
0.100 BSC
0.600 BSC
0.300 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
28
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
2.54 BSC
15.24 BSC
7.62 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
28
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
ccc M C A - B S D S
aaa
M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
α
aaa
bbb
ccc
M
N
5
