PRELIMINARY DATASHEET
SERIAL REAL-TIME CLOCK
Description
The IDT5P90005 is a serial real-time clock (RTC) device
that consumes ultra-low power and provides a full
binary-coded decimal (BCD) clock/calendar. The
clock/calendar provides seconds, minutes, hours, day,
date, month, and year information. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator.
The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections for
leap year. Access to the clock/calendar registers is
provided by an I
2
C interface capable of operating in fast I
2
C
mode. Built-in Power-sense circuitry detects power failures
and automatically switches to the backup supply,
maintaining time and date operation.
IDT5P90005
Features
•
Packaged in 8-pin SOIC
•
Counters for seconds, minutes, hours, days, date,
months, years, and century
•
32 kHz crystal oscillator integrating load capacitance
(12.5 pF) providing exceptional oscillator stability and
high crystal series resistance operation
•
Serial interface supports I2C bus (100 or 400 kHz
protocol)
•
•
•
•
•
Ultra low battery supply current of 0.8 µA (typ at 3 V)
2.0 to 5.5 V clock operating voltage
Automatic switch over and deselect circuitry
Automatic leap year compensation
Operating temperature of -40 to +85°C
Block Diagram
OSCI
OSCO
32.768 kHz
Oscillator and
Divider
1 Hz
MUX/
Buffer
FT/OUT
VCC
GND
V
BAT
SCL
SDA
Power
Control
Control
Logic
Clock, Calendar
Counter
I
2
C
Interface
1 Byte
Control
7 Bytes
Buffer
IDT™
SERIAL REAL-TIME CLOCK
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IDT5P90005
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IDT5P90005
SERIAL REAL-TIME CLOCK
RTC
Pin Assignment
OSCI
OSCO
V
BAT
VSS
1
2
3
4
8
7
6
5
VCC
FT/OUT
SCL
SDA
8-Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
OSCI
OSCO
V
BAT
VSS
SDA
SCL
FT/OUT
VCC
Pin
Type
Input
Output
Power
Power
I/O
Input
Output
Power
Oscillator input.
Oscillator output.
Battery supply voltage.
Connect to ground.
Serial data address input/output.
Serial clock.
Pin Description
Frequency test/output driver (open drain).
Supply voltage.
IDT™
SERIAL REAL-TIME CLOCK
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IDT5P90005
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SERIAL REAL-TIME CLOCK
RTC
Device Operation
The IDT5P90005 clock operates as a slave device on the
serial bus. Access is obtained by implementing a start
condition followed by the correct slave address (D0h). The
8 bytes contained in the device can then be accessed
sequentially in the following order:
1st byte: seconds register
2nd byte: minutes register
3rd byte: century/hours register
4th byte: day register
5th byte: date register
6th byte: month register
7th byte: years register
8th byte: control register
The IDT5P90005 clock continually monitors VCC for an
out-of-tolerance condition. Should VCC fall below VSO, the
device terminates an access in progress and resets the
device address counter. Inputs to the device will not be
recognized at this time, to prevent erroneous data from
being written to the device from an out-of-tolerance system.
When VCC falls below VSO, the device automatically
switches over to the battery and powers down into an ultra
low current mode of operation to conserve battery life. Upon
power-up, the device switches from battery to VCC at VSO
and recognizes inputs.
IDT™
SERIAL REAL-TIME CLOCK
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SERIAL REAL-TIME CLOCK
RTC
I
2
C Serial Data Bus
The IDT5P90005 supports the I
2
C bus protocol. A device
that sends data onto the bus is defined as a transmitter and
a device receiving data as a receiver. The device that
controls the message is called a master. The devices that
are controlled by the master are referred to as slaves. The
bus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The
IDT5P90005 operates as a slave on the I
2
C bus. Within the
bus specifications, a standard mode (100 kHz maximum
clock rate) and a fast mode (400 kHz maximum clock rate)
are defined. The IDT5P90005 works in both modes.
Connections to the bus are made via the open-drain I/O
lines SDA and SCL.
The following bus protocol has been defined (see the “Data
Transfer on I
2
C Serial Bus” figure):
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge:
Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
•
Data transfer may be initiated only when the bus is not
busy.
•
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy:
Both data and clock lines remain HIGH.
Start data transfer:
A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer:
A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid:
The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
not limited, and is determined by the master device. The
IDT™
SERIAL REAL-TIME CLOCK
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SERIAL REAL-TIME CLOCK
RTC
Data Transfer on I
2
C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1)
Data transfer from a master transmitter to a slave
receiver.
The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2)
Data transfer from a slave transmitter to a master
receiver.
The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit. This
is followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
The IDT5P90005 can operate in the following two modes:
1)
Slave Receiver Mode (Write Mode):
Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT5P90005 address, which is
1101000, followed by the direction bit (R/W), which is 0 for
a write. After receiving and decoding the slave address byte
the slave outputs an acknowledge on the SDA line. After the
IDT5P90005 acknowledges the slave address + write bit,
the master transmits a register address to the IDT5P90005.
This sets the register pointer on the IDT5P90005, with the
IDT5P90005 acknowledging the transfer. The master may
then transmit zero or more bytes of data, with the
IDT5P90005 acknowledging each byte received. The
address pointer increments after each data byte is
transferred. The master generates a STOP condition to
terminate the data write.
2)
Slave Transmitter Mode (Read Mode):
The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT5P90005 while the serial clock is input on
SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT5P90005 address, which is 1101000, followed
by the direction bit (R/W), which is 1 for a read. After
receiving and decoding the slave address byte the slave
outputs an acknowledge on the SDA line. The IDT5P90005
IDT™
SERIAL REAL-TIME CLOCK
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IDT5P90005
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