INTEGRATED CIRCUITS
74ALVCH16373
2.5V/3.3V 16-bit D-type transparent latch
(3-State)
Product specification
Supersedes data of 1998 Jun 29
IC24 Data Handbook
1999 Sep 20
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
CMOS low power consumption
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2LE
•
Direct interface with TTL levels
•
All data inputs have bus hold
•
Output drive capability 50Ω transmission lines @ 85°C
•
Current drive
±24
mA at 3.0 V
DESCRIPTION
The 74ALVCH16373 is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. One latch enable (LE) input and one output enable
(OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
SW00066
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5ns
SYMBOL
PARAMETER
Propagation delay
g
y
Dn to Qn
t
PHL
/t
PLH
Propagation delay
g
y
LE to Qn
Input capacitance
Power dissipation capacitance per latch
V
I
= GND to V
CC1
Outputs enabled
Outputs disabled
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
TYPICAL
2.1
2.1
2.2
2.2
5.0
16
10
pF
pF
ns
UNIT
C
I
C
PD
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16373 DL
74ALVCH16373 DGG
NORTH AMERICA
ACH16373 DL
ACH16373 DGG
DWG NUMBER
SOT370-1
SOT362-1
1999 Sep 20
2
853-2086 22418
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 5, 6, 8, 9,
11, 12
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17,
19, 20, 22, 23
24
25
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
48
SYMBOL
1OE
1Q0 to 1Q7
GND
V
CC
2Q0 to 2Q7
2OE
2LE
2D0 to 2D7
1D0 to 1D7
1LE
NAME AND FUNCTION
Output enable input
(active LOW)
LOGIC SYMBOL
1
24
1OE
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Data inputs/outputs
Ground (0V)
Positive supply voltage
Data inputs/outputs
Output enable input
(active LOW)
Latch enable input (active
HIGH)
Data inputs
Data inputs
Latch enable input (active
HIGH)
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1LE
2LE
48
25
SW00067
LOGIC DIAGRAM
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH
1
LE
LE
LATCH
9
LE
LE
1LE
1OE
2LE
2OE
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
SW00068
FUNCTION TABLE
(per section of eight bits)
INPUTS
OPERATING MODES
nOE
Enable and read register
(transparent mode)
Latch and read register
(hold mode)
Latch register and disable outputs
H
h
L
l
X
Z
L
L
L
L
H
H
nLE
H
H
L
L
L
L
nDn
L
H
l
h
l
h
INTERNAL
LATCHES
L
H
L
H
L
H
OUTPUTS
nQn
L
H
L
H
Z
Z
= HIGH voltage level
= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
= don’t care
= high impedance OFF-state
1999 Sep 20
3
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
4D
2
∇
1EN
C3
2EN
C4
3D
1
∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
BUS HOLD CIRCUIT
V
CC
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
Data Input
To internal circuit
SW00044
SW00524
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
For data input pins
V
I
V
O
T
amb
t
r
, t
f
DC Input voltage range
For control pins
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
0
0
–40
0
0
CONDITIONS
MIN
2.3
3.0
0
MAX
2.7
V
3.6
V
CC
5.5
V
CC
+85
20
10
V
°C
ns/V
UNIT
V
1999 Sep 20
4
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC in ut voltage
input
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
2
For data inputs
2
V
O
uV
CC
or V
O
t
0
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
850
600
V
mA
V
mA
mA
°C
mW
UNIT
V
mA
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
CC
= 1.2V
V
IH
HIGH level Input voltage
V
CC
= 1.8V
V
CC
= 2.3 to 2.7V
V
CC
= 2.7 to 3.6V
V
CC
= 1.2V
V
IL
LOW level Input voltage
V
CC
= 1.8V
V
CC
= 2.3 to 2.7V
V
CC
= 2.7 to 3.6V
V
CC
= 1 8 to 3 6V; V
I
= V
IH
or V
IL
; I
O
= –100µA
100µA
1.8 3.6V;
V
CC
= 1.8V; V
I
= V
IH
or V
IL
; I
O
= –6mA
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= –6mA
V
OH
HIGH level output voltage
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= –18mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
*0.2
02
V
CC*
0.4
V
CC*
0.3
V
CC*
0.5
V
CC*
0.6
V
CC*
0.5
V
CC
*1.0
0.9
1.2
1.5
V
CC
V
CC*
0.10
V
CC*
0.08
V
CC*
0.17
V
CC*
0.26
V
CC*
0.14
V
CC*
0.28
V
V
CC
0.7*V
CC
1.7
2.0
0.9
V
1.2
1.5
GND
0.2*V
CC
0.7
0.8
V
TYP
1
MAX
UNIT
1999 Sep 20
5
