74AUP1G0832
Low-power 3-input AND-OR gate
Rev. 01.00 — 26 January 2006
Preliminary data sheet
1. General description
The 74AUP1G0832 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G0832 provides the Boolean function: Y = (A
×
B) + C. The user can choose
the logic functions OR, AND and AND-OR. All inputs can be connected to V
CC
or GND.
2. Features
s
Wide supply voltage range from 0.8 V to 3.6 V
s
High noise immunity
s
Complies with JEDEC standards:
x
JESD8-12 (0.8 V to 1.3 V)
x
JESD8-11 (0.9 V to 1.65 V)
x
JESD8-7 (1.2 V to 1.95 V)
x
JESD8-5 (1.8 V to 2.7 V)
x
JESD8-B (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114-C Class 3A. Exceeds 5000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101-C exceeds 1000 V
s
Low static power consumption; I
CC
= 0.9
µA
(maximum)
s
Latch-up performance exceeds 100 mA per JESD 78 Class II
s
Inputs accept voltages up to 3.6 V
s
Low noise overshoot and undershoot < 10 % of V
CC
s
I
OFF
circuitry provides partial Power-down mode operation
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
Philips Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3 ns.
Symbol
Parameter
Conditions
C
L
= 5 pF; R
L
= 1 MΩ;
V
CC
= 0.8 V
C
L
= 5 pF; R
L
= 1 MΩ;
V
CC
= 1.1 V to 1.3 V
C
L
= 5 pF; R
L
= 1 MΩ;
V
CC
= 1.4 V to 1.6 V
C
L
= 5 pF; R
L
= 1 MΩ;
V
CC
= 1.65 V to 1.95 V
C
L
= 5 pF; R
L
= 1 MΩ;
V
CC
= 2.3 V to 2.7 V
C
L
= 5 pF; R
L
= 1 MΩ;
V
CC
= 3.0 V to 3.6 V
C
I
C
PD
input capacitance
power dissipation
capacitance
V
CC
= 1.8 V; f = 1 MHz
V
CC
= 3.3 V; f = 1 MHz
[1] [2]
[1] [2]
Min
-
2.5
1.9
1.6
1.4
1.3
-
-
-
Typ
19.5
5.6
3.9
3.1
2.4
2.2
1.0
3.3
4.2
Max
-
11.1
6.4
5.1
3.7
3.2
-
-
-
Unit
ns
ns
ns
ns
ns
ns
pF
pF
pF
t
PHL
, t
PLH
HIGH-to-LOW and
LOW-to-HIGH
propagation delay
A, B or C to Y
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74AUP1G0832GW
74AUP1G0832GM
74AUP1G0832GF
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SC-88
XSON6
XSON6
Description
plastic surface mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
×
1
×
0.5 mm
74AUP1G0832_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
2 of 19
Philips Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
5. Marking
Table 3:
Marking
Marking code
aY
aY
aY
Type number
74AUP1G0832GW
74AUP1G0832GM
74AUP1G0832GF
6. Functional diagram
1
3
6
4
Y
A
B
C
001aad943
Fig 1. Logic symbol
7. Pinning information
7.1 Pinning
74AUP1G0832
74AUP1G0832
A
GND
1
2
6
5
C
GND
V
CC
B
B
3
001aad940
A
1
6
C
2
5
V
CC
3
4
Y
4
Y
001aad941
Transparent top view
Fig 2. Pin configuration SOT363 (SC-88)
Fig 3. Pin configuration SOT886 (XSON6)
74AUP1G0832
A
GND
B
1
2
3
6
5
4
C
V
CC
Y
001aad942
Transparent top view
Fig 4. Pin configuration SOT891 (XSON6)
74AUP1G0832_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
3 of 19
Philips Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
7.2 Pin description
Table 4:
Symbol
A
GND
B
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input A
ground (0 V)
data input B
data output Y
supply voltage
data input C
8. Functional description
8.1 Function table
Table 5:
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
L
H
H
H
H
H
H = HIGH voltage level;
L = LOW voltage level.
8.2 Logic configurations
Table 6:
Function selection table
Figure
see
Figure 5
see
Figure 6
and
7
see
Figure 8
Logic function
2-input AND
2-input OR
3-input gate with the Boolean function:
Y = (A
×
B) + C
74AUP1G0832_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
4 of 19
Philips Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
V
CC
A
B
B
C
Y
A
B
1
2
3
6
5
4
001aad944
Y
B
V
CC
Y
1
2
3
6
5
4
001aad945
C
Y
Fig 5. 2-input AND gate
Fig 6. 2-input OR gate
V
CC
A
C
Y
A
1
2
3
6
5
4
C
Y
A
B
C
V
CC
Y
A
B
1
2
3
6
5
4
C
Y
001aad946
001aad947
Fig 7. 2-input OR gate
Fig 8. 3-input gate with the Boolean
function: Y = (A
×
B) + C
9. Limiting values
Table 7:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping
current
input voltage
output clamping
current
output voltage
output current
quiescent supply
current
ground current
storage temperature
total power
dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
-
−0.5
-
[1]
Max
+4.6
−50
+4.6
−50
+4.6
±20
+50
−50
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
< 0 V
active mode and
Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
-
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are
observed.
For SC-88 packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
74AUP1G0832_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
5 of 19
