D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
74F113 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised September 2000
74F113
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip-
flop will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock
pulse.
Asynchronous input:
LOW input to S
D
sets Q to HIGH level
Set is independent of clock
Ordering Code:
Order Number
74F113SC
74F113SJ
74F113PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009473
www.fairchildsemi.com
74F113
Unit Loading/Fan Out
U.L.
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
, Q
2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
Description
HIGH/LOW
1.0/1.0
1.0/4.0
1.0/5.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
2.4 mA
20
µ
A/
−
3.0 mA
−
1 mA/20 mA
Truth Table
Inputs
S
D
L
H
H
H
H
CP
J
X
h
l
h
l
K
X
h
h
l
l
Outputs
Q
H
Q
0
L
H
Q
0
Q
L
Q
0
H
L
Q
0
H (h)
=
HIGH Voltage Level
L (l)
=
LOW Voltage level
]
=
HIGH-to-LOW Clock Transition
X
=
Immaterial
Q
0
(Q
0
)
=
Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
X
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74F113
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
4.75
3.75
−0.6
−2.4
−3.0
I
OZH
I
OZL
I
OS
I
CC
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
−60
12
50
−50
−150
19
µA
µA
mA
mA
Max
Max
Max
Max
mA
Max
5.0
7.0
50
µA
µA
µA
V
µA
Max
Max
Max
0.0
0.0
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (J
n
, K
n
)
V
IN
=
0.5V (CP
n
)
V
IN
=
0.5V (S
Dn
)
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
Min
Min
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
3
www.fairchildsemi.com
74F113
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
S
Dn
to Q
n
or Q
n
85
2.0
2.0
2.0
2.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
105
4.0
4.0
4.5
4.5
6.0
6.0
6.5
6.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
80
2.0
2.0
2.0
2.0
7.0
7.0
7.5
7.5
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
J
n
or K
n
to CP
n
Hold Time, HIGH or LOW
J
n
or K
n
to CP
n
CP
n
Pulse Width
HIGH or LOW
S
Dn
Pulse Width, LOW
S
Dn
to CP
n
Recovery Time
4.0
3.0
0
0
4.5
4.5
4.5
4.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
5.0
3.5
0
0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
Max
Units
www.fairchildsemi.com
4
