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74FCT388915TCJG

PLCC-28, Tube

器件类别：逻辑    逻辑   

厂商名称：IDT (Integrated Device Technology)

器件标准：  

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器件参数
参数名称
属性值
Brand Name
Integrated Device Technology
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
IDT (Integrated Device Technology)
零件包装代码
PLCC
包装说明
QCCJ, LDCC28,.5SQ
针数
28
制造商包装代码
PLG28
Reach Compliance Code
compliant
ECCN代码
EAR99
其他特性
OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS
系列
FCT
输入调节
SCHMITT TRIGGER MUX
JESD-30 代码
S-PQCC-J28
JESD-609代码
e3
长度
11.5062 mm
逻辑集成电路类型
PLL BASED CLOCK DRIVER
最大I（ol）
0.032 A
湿度敏感等级
1
功能数量
1
反相输出次数
1
端子数量
28
实输出次数
7
最高工作温度
70 °C
最低工作温度
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC28,.5SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
峰值回流温度（摄氏度）
260
电源
3.3 V
传播延迟（tpd）
1.3 ns
认证状态
Not Qualified
Same Edge Skew-Max（tskwd）
0.8 ns
座面最大高度
4.572 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Matte Tin (Sn) - annealed
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
11.5062 mm
最小 fmax
100 MHz
文档预览
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x output, one
÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Duty cycle distortion < 500ps (max.)
• 32/–16mA drive at CMOS output voltage levels
• V
CC
= 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC and SSOP packages
•
NOT RECOMMENDED FOR NEW DESIGNS
•
For functional replacement use 8T49N286A
IDT74FCT388915T
70/100/133/150
FEATURES:
The FCT388915T uses phase-lock loop technology to lock the fre-
quency and phase of outputs to the input reference clock. It provides low
skew clock distribution for high performance PCs and workstations. One
of the outputs is fed back to the PLL at the FEEDBACK input resulting
in essentially zero delay across the device. The PLL consists of the
phase/frequency detector, charge pump, loop
fi
lter and VCO. The VCO
is designed for a 2Q operating frequency range of 40MHz to f2Q Max.
The FCT388915T provides 8 outputs, the
Q5
output is inverted from
the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at
half the Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the
output path. PLL _EN allows bypassing of the PLL, which is useful in
static test modes. When PLL_EN is low, SYNC input may be used as
a test clock. In this test mode, the input frequency is not limited to the
specified range and the polarity of outputs is complementary to that in
normal operation (PLL_EN = 1). The LOCK output attains logic HIGH
when the PLL is in steady-state phase and frequency lock. When OE/
RST
is low, all the outputs are put in high impedance state and registers
at Q,
Q
and Q/2 outputs are reset.
The FCT388915T requires one external loop
fi
lter component as
recommended in Figure 3.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
MARCH 2016
DSC-4243/7
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
SSOP
TOP VIEW
PLCC
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
FREQ_SEL
FEEDBACK
LF
Q0-Q4
Q5
2Q
Q/2
LOCK
OE/RST
PLL_EN
I/O
I
I
I
I
I
I
O
O
O
O
O
I
I
Reference clock input
Reference clock input
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram)
Feedback input to phase detector
Input for external loop
fi
lter connection
Clock output
Inverted clock output
Clock output (2 x Q frequency)
Clock output (Q frequency ÷ 2)
Indicates phase lock has been achieved (HIGH when locked)
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in
HIGH impedance.
Disables phase-lock for low frequency testing (refer to functional block diagram)
Description
2
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
V
TERM
V
TERM
T
STG
I
OUT
(2)
(3)
CAPACITANCE
Unit
V
V
V
°C
mA
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
(T
A
= +25°C, F = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Unit
pF
pF
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +4.6
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Output Capacitance
(4)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 3.3V ± 0.3V
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
V
OL
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(4)
(3-State Output Pins)
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Min., V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min., V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min
V
CC
= Min
—
V
CC
= Max.,V
IN
= GND or V
CC
(Test Mode)
I
OH
= –16mA
I
OL
= 32mA
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= GND
V
I
= V
CC
V
I
= GND
Min.
2
—
—
—
—
—
—
–36
50
2.4
(4)
Typ.
(2)
—
—
—
—
—
—
–0.7
—
—
3.3
0.3
100
2
Max.
5.5
0.8
±1
±1
±1
±1
–1.2
—
—
—
0.5
—
6
Unit
V
V
μA
μA
μA
V
mA
mA
V
V
mV
μA
—
—
—
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. V
OH
= V
CC
- 0.6V at rated current.
3
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
C
PD
I
C
Parameter
Quiescent Power Supply Current
Dynamic Power Supply Current
(4)
Power Dissipation Capacitance
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
–2.1V
(3)
V
CC
= Max.
All Outputs Open
50% Duty Cycle
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with 15pF
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with 50Ω Thevenin
termination and 20pF
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+ DI
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q Frequency
I
LOAD
= Dynamic Current due to load.
Test Conditions
(1)
V
IN
= V
CC
–0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
—
—
—
—
Typ.
(2)
2
0.2
15
30
Max.
30
0.3
25
60
Unit
μA
mA/
MHz
pF
mA
TTL Inputs HIGH
—
90
120
mA
SYNCH INPUT TIMING
REQUIRMENTS
Symbol
Parameter
(0.8V to 2V)
Frequency Input Frequency, SYNC Inputs
Duty Cycle Input Duty Cycle, SYNC Inputs
10
(1)
25%
2Q fmax
75%
MHz
—
Min.
—
Max.
3
Unit
ns
T
RISE/FALL
Rise/Fall Times, SYNC inputs
OUTPUT FREQUENCY SPECIFICATIONS
Max.
(2)
Symbol
f2Q
fQ
fQ/2
Parameter
Operating frequency 2Q Output
Operating frequency Q0-Q4,
Q5
Outputs
Operating frequency Q/2 Output
Min.
40
20
10
70
70
35
17.5
100
100
50
25
133
(3)
133
66.7
33.3
150
(3)
150
75
37.5
Unit
MHz
MHz
MHz
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
3. At this frequency, 2Q cannot be used as feedback.
4
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition
(1)
t
RISE/FALL
All Outputs
t
PULSE WIDTH
(3)
Q,
Q,
Q/2 outputs
(3)
t
PULSE WIDTH
2Q Output
(3)
t
PD
SYNC-FEEDBACK
(3)
t
SKEW
r
(rising)
(3,4)
t
SKEW
f
(falling)
(3,4)
t
SKEW
all
(3,4)
t
LOCK
(6)
t
PZH
t
PZL
t
PHZ
t
PLZ
Rise/Fall Time
(between 0.8V and 2V)
Output Pulse Width
Q0-Q4,
Q5,
Q/2, @ 1.5V
Output Pulse Width
2Q @ 1.5V
SYNC input to FEEDBACK delay
Output to Output Skew between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
Time required to acquire Phase-Lock from time
SYNC input signal is received
Output Enable Time
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2,
Q
Output Disable Time
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2,
Q
Load = 50Ω to V
CC
/2, C
L
= 20pF
Load = 50Ω to V
CC
/2, C
L
= 20pF
Load = 50Ω to V
CC
/2, C
L
= 20pF
Load = 50Ω to V
CC
/2, C
L
= 20pF
Min.
0.2
(2)
Max.
2
Unit
ns
ns
ns
ns
ps
ps
ps
ms
ns
ns
0.5t
CYCLE
– 0.8
(5)
0.5t
CYCLE
+ 0.8
(5)
0.5t
CYCLE
– 1
(5)
+0.1
—
—
—
1
(2)
3
(2)
3
(2)
0.5t
CYCLE
+ 1
(5)
+1.3
600
250
800
10
14
14
(measured at SYNC0 or 1 and FEEDBACK input pins) 0.1μF from LF to Analog GND
(5)
2Q, Q/2, Q0-Q4 rising,
Q5
falling
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a
fi
xed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q,
Q,
Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin, t
LOCK
Max. is with C1 = 0.1μF, t
LOCK
Min. is with C1 = 0.01μF. (Where C1 is loop
fi
lter capacitor
shown in Figure 2).
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC
input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW. Also it is
possible to feed back the
Q5
output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC frequency range for
each possible configuration.
FREQ_SEL
Level
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Feedback
Output
Q/2
Any Q (Q0-Q4)
Q5
2X_Q
Q/2
Any Q (Q0-Q4)
Q5
2X_Q
Allowable SYNC Input
Frequency Range (MHZ)
10 to (2x_Q f
MAX
Spec)/4
20 to (2x_Q f
MAX
Spec)/2
20 to (2x_Q f
MAX
Spec)/2
40 to (2x_Q f
MAX
Spec)
5 to (2x_Q f
MAX
Spec)/8
10 to (2x_Q f
MAX
Spec)/4
10 to (2x_Q f
MAX
Spec)/4
20 to (2x_Q f
MAX
Spec)/2
Corresponding 2Q Output
Frequency Range
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
Phase Relationship of the Q Outputs
to Rising SYNC Edge
0°
0°
180°
0°
0°
0°
180°
0°
5
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参数对比
与74FCT388915TCJG相近的元器件有：74FCT388915TDPYG8、74FCT388915TDPYG、74FCT388915TBPYG8、74FCT388915TDJG8、74FCT388915TDJG、74FCT388915TCPYG8、74FCT388915TCJG8、74FCT388915TBPYG、74FCT388915TBJG。描述及对比如下：
型号 74FCT388915TCJG 74FCT388915TDPYG8 74FCT388915TDPYG 74FCT388915TBPYG8 74FCT388915TDJG8 74FCT388915TDJG 74FCT388915TCPYG8 74FCT388915TCJG8 74FCT388915TBPYG 74FCT388915TBJG
描述 PLCC-28, Tube SSOP-28, Reel SSOP-28, Tube SSOP-28, Reel PLCC-28, Reel PLCC-28, Tube SSOP-28, Reel PLCC-28, Reel SSOP-28, Tube PLCC-28, Tube
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology
是否无铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅 不含铅
是否Rohs认证 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合
零件包装代码 PLCC SSOP SSOP SSOP PLCC PLCC SSOP PLCC SSOP PLCC
包装说明 QCCJ, LDCC28,.5SQ GREEN, SSOP-28 SSOP, SSOP28,.3 GREEN, SSOP-28 PLASTIC, LCC-28 QCCJ, LDCC28,.5SQ GREEN, SSOP-28 GREEN, PLASTIC, LCC-28 SSOP, SSOP28,.3 QCCJ, LDCC28,.5SQ
针数 28 28 28 28 28 28 28 28 28 28
制造商包装代码 PLG28 PYG28 PYG28 PYG28 PLG28 PLG28 PYG28 PLG28 PYG28 PLG28
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
系列 FCT FCT FCT FCT FCT FCT FCT FCT FCT FCT
输入调节 SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX SCHMITT TRIGGER MUX
JESD-30 代码 S-PQCC-J28 R-PDSO-G28 R-PDSO-G28 R-PDSO-G28 S-PQCC-J28 S-PQCC-J28 R-PDSO-G28 S-PQCC-J28 R-PDSO-G28 S-PQCC-J28
JESD-609代码 e3 e3 e3 e3 e3 e3 e3 e3 e3 e3
长度 11.5062 mm 10.2 mm 10.2 mm 10.2 mm 11.5062 mm 11.5062 mm 10.2 mm 11.5062 mm 10.2 mm 11.5062 mm
逻辑集成电路类型 PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
最大I（ol） 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A
湿度敏感等级 1 1 1 1 1 1 1 1 1 1
功能数量 1 1 1 1 1 1 1 1 1 1
反相输出次数 1 1 1 1 1 1 1 1 1 1
端子数量 28 28 28 28 28 28 28 28 28 28
实输出次数 7 7 7 7 7 7 7 7 7 7
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QCCJ SSOP SSOP SSOP QCCJ QCCJ SSOP QCCJ SSOP QCCJ
封装等效代码 LDCC28,.5SQ SSOP28,.3 SSOP28,.3 SSOP28,.3 LDCC28,.5SQ LDCC28,.5SQ SSOP28,.3 LDCC28,.5SQ SSOP28,.3 LDCC28,.5SQ
封装形状 SQUARE RECTANGULAR RECTANGULAR RECTANGULAR SQUARE SQUARE RECTANGULAR SQUARE RECTANGULAR SQUARE
封装形式 CHIP CARRIER SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH CHIP CARRIER CHIP CARRIER SMALL OUTLINE, SHRINK PITCH CHIP CARRIER SMALL OUTLINE, SHRINK PITCH CHIP CARRIER
峰值回流温度（摄氏度） 260 260 260 260 260 260 260 260 260 260
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
传播延迟（tpd） 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.8 ns 0.8 ns 0.8 ns 0.8 ns 0.8 ns 0.8 ns 0.8 ns 0.8 ns 0.8 ns 0.8 ns
座面最大高度 4.572 mm 2 mm 1.99 mm 2 mm 4.572 mm 4.572 mm 2 mm 4.572 mm 1.99 mm 4.572 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
端子形式 J BEND GULL WING GULL WING GULL WING J BEND J BEND GULL WING J BEND GULL WING J BEND
端子节距 1.27 mm 0.65 mm 0.65 mm 0.65 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm 0.65 mm 1.27 mm
端子位置 QUAD DUAL DUAL DUAL QUAD QUAD DUAL QUAD DUAL QUAD
处于峰值回流温度下的最长时间 NOT SPECIFIED 30 30 30 NOT SPECIFIED NOT SPECIFIED 30 NOT SPECIFIED 30 NOT SPECIFIED
宽度 11.5062 mm 5.3 mm 5.3 mm 5.3 mm 11.5062 mm 11.5062 mm 5.3 mm 11.5062 mm 5.3 mm 11.5062 mm
最小 fmax 100 MHz 133 MHz 133 MHz 70 MHz 133 MHz 133 MHz 100 MHz 100 MHz 70 MHz 70 MHz
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) - IDT (Integrated Device Technology) IDT (Integrated Device Technology)
其他特性 OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS - OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS - OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS
Base Number Matches - 1 1 1 1 1 1 1 - -
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