INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT10
Triple 3-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Triple 3-input NAND gate
FEATURES
•
Output capability: standard
•
I
CC
category: SSI
GENERAL DESCRIPTION
74HC/HCT10
The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT10 provide the 3-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
O
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nA, nB, nC to nY
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
9
3.5
12
11
3.5
14
HCT
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Triple 3-input NAND gate
PIN DESCRIPTION
PIN NO.
1, 3, 9
2, 4, 10
13, 5, 11
12, 6, 8
7
14
SYMBOL
1A to 3A
1B to 3B
1C to 3C
1Y to 3Y
GND
V
CC
NAME AND FUNCTION
data inputs
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
74HC/HCT10
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
nA
L
L
L
L
H
H
H
H
Notes
Fig.4 Functional diagram.
Fig.5 Logic diagram (one gate).
1. H = HIGH voltage level
L = LOW voltage level
nB
L
L
H
H
L
L
H
H
nC
L
H
L
H
L
H
L
H
OUTPUT
nY
H
H
H
H
H
H
H
L
December 1990
3
Philips Semiconductors
Product specification
Triple 3-input NAND gate
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
min.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC to nY
typ.
30
11
9
t
THL
/ t
TLH
output transition time
19
7
6
−40
to + 85
max. min.
95
19
16
75
15
13
max.
120
24
20
95
19
16
−40
to + 125
min.
max.
145
29
25
110
22
19
ns
ns
UNIT
74HC/HCT10
TEST CONDITIONS
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
Fig.6
WAVEFORMS
December 1990
4
Philips Semiconductors
Product specification
Triple 3-input NAND gate
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
Note to HCT types
74HC/HCT10
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine
∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
nA, nB, nC
UNIT LOAD COEFFICIENT
1.5
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HCT
SYMBOL PARAMETER
+ 25
min.
t
PHL
/ t
PLH
t
THL
/ t
TLH
propagation delay
nA, nB, nC to nY
output transition time
typ.
14
7
max.
24
15
−40
to + 85
min.
max.
30
19
−40
to +125
min.
max.
36
22
ns
ns
4.5
4.5
Fig.6
Fig.6
UNIT
V
CC
(V)
WAVEFORMS
TEST CONDITIONS
AC WAVEFORMS
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
5
