74HCT161N,74HCT161N pdf中文资料,74HCT161N引脚图,74HCT161N电路-Datasheet-电子工程世界

器件参数

参数名称

属性值

Source Url Status Check Date

2013-06-14 00:00:00

是否无铅

不含铅

是否Rohs认证

符合

厂商名称

NXP(恩智浦)

零件包装代码

DIP

包装说明

DIP, DIP16,.3

针数

Reach Compliance Code

unknown

ECCN代码

EAR99

其他特性

TCO OUTPUT

计数方向

系列

HCT

JESD-30 代码

R-PDIP-T16

JESD-609代码

长度

21.6 mm

负载电容（CL）

50 pF

负载/预设输入

YES

逻辑集成电路类型

BINARY COUNTER

最大频率@ Nom-Sup

18000000 Hz

最大I（ol）

0.004 A

工作模式

SYNCHRONOUS

位数

功能数量

端子数量

最高工作温度

125 °C

最低工作温度

-40 °C

封装主体材料

PLASTIC/EPOXY

封装代码

DIP

封装等效代码

DIP16,.3

封装形状

RECTANGULAR

封装形式

IN-LINE

峰值回流温度（摄氏度）

NOT APPLICABLE

电源

5 V

传播延迟（tpd）

65 ns

认证状态

Not Qualified

座面最大高度

4.7 mm

最大供电电压 (Vsup)

5.5 V

最小供电电压 (Vsup)

4.5 V

标称供电电压 (Vsup)

5 V

表面贴装

技术

CMOS

温度等级

AUTOMOTIVE

端子面层

NICKEL PALLADIUM GOLD

端子形式

THROUGH-HOLE

端子节距

2.54 mm

端子位置

DUAL

处于峰值回流温度下的最长时间

NOT APPLICABLE

触发器类型

POSITIVE EDGE

宽度

7.62 mm

最小 fmax

15 MHz

Base Number Matches

文档预览

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

•

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT161

Presettable synchronous 4-bit

binary counter; asynchronous reset

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous 4-bit binary

counter; asynchronous reset

FEATURES

•

Synchronous counting and loading

•

Two count enable inputs for n-bit cascading

•

Positive-edge triggered clock

•

Asynchronous reset

•

Output capability: standard

•

category: MSI

GENERAL DESCRIPTION

The 74HC/HCT161 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT161 are synchronous presettable binary

counters which feature an internal look-ahead carry and

can be used for high-speed counting.

Synchronous operation is provided by having all flip-flops

clocked simultaneously on the positive-going edge of the

clock (CP).

The outputs (Q

to Q

) of the counters may be preset to a

HIGH or LOW level. A LOW level at the parallel enable

74HC/HCT161

input (PE) disables the counting action and causes the

data at the data inputs (D

to D

) to be loaded into the

counter on the positive-going edge of the clock (providing

that the set-up and hold time requirements for PE are met).

Preset takes place regardless of the levels at count enable

inputs (CEP and CET).

A LOW level at the master reset input (MR) sets all four

outputs of the flip-flops (Q

to Q

) to LOW level regardless

of the levels at CP, PE, CET and CEP inputs (thus

providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the

counters. Both count enable inputs (CEP and CET) must

be HIGH to count. The CET input is fed forward to enable

the terminal count output (TC). The TC output thus

enabled will produce a HIGH output pulse of a duration

approximately equal to a HIGH level output of Q

. This

pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters

is determined by the CP to TC propagation delay and CEP

to CP set-up time, according to the following formula:

max

= --------------------------------------------------------------------------------------------------

P(max)

(CP to TC)

(CEP to CP)

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25

°C;

= t

= 6 ns

TYPICAL

SYMBOL PARAMETER

PHL

/ t

PLH

propagation delay

CP to Q

CP to TC

MR to Q

MR to TC

CET to TC

maximum clock frequency

input capacitance

power dissipation

capacitance per package

notes 1 and 2

CONDITIONS

= 15 pF;

= 5 V

3.5

HCT

3.5

MHz

UNIT

Notes

1. C

is used to determine the

dynamic power dissipation

µW):

= C

CC2

∑

CC2

)

where:

= input frequency in MHz

= output frequency in MHz

∑

CC2

) = sum of

outputs

= output load capacitance in

= supply voltage in V

2. For HC the condition is

= GND to V

For HCT the condition is

= GND to V

−

1.5 V

max

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous 4-bit binary

counter; asynchronous reset

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

PIN DESCRIPTION

PIN NO.

3, 4, 5, 6

14, 13, 12, 11

SYMBOL

to D

CEP

GND

CET

to Q

NAME AND FUNCTION

asynchronous master reset (active LOW)

clock input (LOW-to-HIGH, edge-triggered)

data inputs

count enable input

ground (0 V)

parallel enable input (active LOW)

count enable carry input

ﬂip-ﬂop outputs

terminal count output

positive supply voltage

74HC/HCT161

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous 4-bit binary

counter; asynchronous reset

74HC/HCT161

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS

OPERATING MODE

reset (clear)

parallel load

count

hold

(do nothing)

Note

1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition

q = lower case letters indicate the state of the referenced output one set-up time prior to the

LOW-to-HIGH CP transition

X = don’t care

↑

= LOW-to-HIGH CP transition

↑

CEP

CET

count

(1)

OUTPUTS

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous 4-bit binary

counter; asynchronous reset

74HC/HCT161

Fig.5 State diagram.

Fig.6

Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen,

zero, one and two; inhibit.

December 1990

参数对比

与74HCT161N相近的元器件有：74HC161D-AUJ、74HCT161PW、74HC161PW-T、74HCT161D-T、74HC161DB-T、74HCT161DB。描述及对比如下：

型号	74HCT161N	74HC161D-AUJ	74HCT161PW	74HC161PW-T	74HCT161D-T	74HC161DB-T	74HCT161DB
描述	Counter ICs SYNC 4-BIT BINARY COUNTER	Counter ICs Presettable synchrns 4-bit binary counter	Counter ICs SYNC 4-BIT BINARY COUNTER	Counter ICs SYNC 4-BIT BINARY COUNTER	Counter ICs SYNC 4-BIT BINARY COUNTER	Counter ICs SYNC 4-BIT BINARY COUNTER	Counter ICs SYNC 4-BIT BINARY COUNTER
Source Url Status Check Date	2013-06-14 00:00:00	-	-	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00	-
是否Rohs认证	符合	-	符合	符合	符合	符合	符合
厂商名称	NXP(恩智浦)	-	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	DIP	-	TSSOP	TSSOP	SOIC	SOIC	SOIC
包装说明	DIP, DIP16,.3	-	SOT403-1, TSSOP-16	TSSOP,	3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16	SSOP,	SOT338-1, SSOP-16
针数	16	-	16	16	16	16	16
Reach Compliance Code	unknown	-	unknown	unknown	unknown	unknown	unknown
其他特性	TCO OUTPUT	-	TCO OUTPUT	TCO OUTPUT	TCO OUTPUT	TCO OUTPUT	TCO OUTPUT
计数方向	UP	-	UP	UP	UP	UP	UP
系列	HCT	-	HCT	HC/UH	HCT	HC/UH	HCT
JESD-30 代码	R-PDIP-T16	-	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609代码	e4	-	e4	e4	e4	e4	e4
长度	21.6 mm	-	5 mm	5 mm	9.9 mm	6.2 mm	6.2 mm
负载电容（CL）	50 pF	-	50 pF	50 pF	50 pF	50 pF	50 pF
负载/预设输入	YES	-	YES	YES	YES	YES	YES
逻辑集成电路类型	BINARY COUNTER	-	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
工作模式	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
位数	4	-	4	4	4	4	4
功能数量	1	-	1	1	1	1	1
端子数量	16	-	16	16	16	16	16
最高工作温度	125 °C	-	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-40 °C	-	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	DIP	-	TSSOP	TSSOP	SOP	SSOP	SSOP
封装形状	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	NOT APPLICABLE	-	260	260	260	260	260
传播延迟（tpd）	65 ns	-	65 ns	285 ns	65 ns	57 ns	65 ns
认证状态	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	4.7 mm	-	1.1 mm	1.1 mm	1.75 mm	2 mm	2 mm
最大供电电压 (Vsup)	5.5 V	-	5.5 V	6 V	5.5 V	6 V	5.5 V
最小供电电压 (Vsup)	4.5 V	-	4.5 V	2 V	4.5 V	2 V	4.5 V
标称供电电压 (Vsup)	5 V	-	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	-	YES	YES	YES	YES	YES
技术	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
端子面层	NICKEL PALLADIUM GOLD	-	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
端子形式	THROUGH-HOLE	-	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	2.54 mm	-	0.65 mm	0.65 mm	1.27 mm	0.65 mm	0.65 mm
端子位置	DUAL	-	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT APPLICABLE	-	30	30	30	30	30
触发器类型	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
宽度	7.62 mm	-	4.4 mm	4.4 mm	3.9 mm	5.3 mm	5.3 mm
最小 fmax	15 MHz	-	15 MHz	15 MHz	15 MHz	15 MHz	15 MHz
Base Number Matches	1	-	1	1	1	1	1
湿度敏感等级	-	-	1	1	1	1	1