74HC259; 74HCT259
8-bit addressable latch
Rev. 6 — 2 February 2016
Product data sheet
1. General description
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes
of operation. In the addressable latch mode, data on the D input is written into the latch
addressed by the inputs AO to A3. The addressed latch will follow the data input,
non-addressed latches will retain their previous states. In memory mode, all latches retain
their previous states and are unaffected by the data or address inputs. In the 3-to-8
decoding or demultiplexing mode, the addressed output follows the D input and all other
outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the
data or address inputs. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Complies with JEDEC standard no. 7A
Input levels:
For 74HC259: CMOS level
For 74HCT259: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Nexperia
74HC259; 74HCT259
8-bit addressable latch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC259D
74HCT259D
74HC259DB
74HCT259DB
74HC259PW
74HCT259PW
74HC259BQ
74HCT259BQ
40 C
to +125
C
DHVQFN16
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 6 — 2 February 2016
©
2 of 21
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC259; 74HCT259
8-bit addressable latch
Fig 3.
Functional diagram
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO16, SSOP16 and
TSSOP16
Fig 5.
Pin configuration DHVQFN16
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 6 — 2 February 2016
©
3 of 21
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC259; 74HCT259
8-bit addressable latch
5.2 Pin description
Table 2.
Symbol
A0, A1, A2
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
D
LE
MR
V
CC
Pin description
Pin
1, 2, 3
4, 5, 6, 7, 9, 10, 11, 12
8
13
14
15
16
Description
address input
latch output
ground (0 V)
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
6. Functional description
Table 3.
Function table
[1]
Input
MR
Reset (clear)
L
L
Demultiplexer
(active HIGH 8-channel) L
decoder (when D = H)
L
L
L
L
L
L
Memory (no action)
Addressable latch
H
H
H
H
H
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Operating mode
Output
LE
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
d
A0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
A1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
A2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
Q0
L
L
L
L
L
L
L
L
q
0
q
0
q
0
q
0
q
0
q
0
q
0
q
0
Q1
L
Q2
L
L
Q3
L
L
L
Q4
L
L
L
L
Q5
L
L
L
L
L
Q6
L
L
L
L
L
L
Q7
L
L
L
L
L
L
L
Q=d
q
7
q
7
q
7
q
7
q
7
q
7
q
7
Q=d
Q=d L
L
L
L
L
L
L
q
1
Q=d L
L
L
L
L
L
q
2
q
2
Q=d L
L
L
L
L
q
3
q
3
q
3
Q=d L
L
L
L
q
4
q
4
q
4
q
4
Q=d L
L
L
q
5
q
5
q
5
q
5
q
5
Q=d L
L
q
6
q
6
q
6
q
6
q
6
q
6
Q=d L
Q = d q
1
q
1
q
1
q
1
q
1
q
1
q
1
Q = d q
2
q
2
q
2
q
2
q
2
q
2
Q = d q
3
q
3
q
3
q
3
q
3
Q = d q
4
q
4
q
4
q
4
Q = d q
5
q
5
q
5
Q = d q
6
q
6
Q = d q
7
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 6 — 2 February 2016
©
4 of 21
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC259; 74HCT259
8-bit addressable latch
Table 4.
LE
L
H
L
H
[1]
Operating mode select table
[1]
MR
H
H
L
L
Mode
Addressable latch mode
Memory mode
Demultiplexer mode
Reset mode
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
[2]
[3]
[4]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
70
65
-
-
-
Max
+7.0
20
20
25
+70
-
+150
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 6 — 2 February 2016
©
5 of 21
Nexperia B.V. 2017. All rights reserved
