74HC597; 74HCT597
8-bit shift register with input flip-flops
Rev. 3 — 15 April 2014
Product data sheet
1. General description
The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an
8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage
register and the shift register have positive edge-triggered clocks. The shift register also
has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable
the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC597: CMOS level
For 74HCT597: TTL level
8-bit parallel storage register inputs
Shift register has direct overriding load and clear
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC5974N
74HCT597N
74HC597D
74HCT597D
74HC597DB
74HCT597DB
74HC597PW
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC Logic symbol
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
2 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
Fig 4.
Logic diagram
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
3 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration DIP16 and SO16
Fig 6.
Pin configuration SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
GND
Q
MR
SHCP
STCP
PL
DS
D0, D1, D2, D3,
D4, D5, D6, D7
V
CC
Pin description
Pin
8
9
10
11
12
13
14
15, 1, 2, 3, 4, 5, 6, 7
16
Description
ground (0 V)
serial data output
asynchronous master reset input (active LOW)
shift register clock input (LOW-to-HIGH, edge-triggered)
storage register clock input (LOW-to-HIGH, edge-triggered)
parallel load input (active LOW)
serial data input
parallel data inputs
supply voltage
74HC_HCT597
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
4 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
6. Functional description
Table 3.
Inputs
STCP
no clock edge
X
X
X
[1]
Function table
[1]
Function
SHCP
X
X
X
X
X
PL
X
L
L
L
H
H
MR
X
H
H
L
L
H
data loaded to input latches
data loaded from inputs to shift register
data transferred from input flip-flops to shift register
invalid logic, state of shift register is indeterminate
when signals removed
shift register cleared
shift register clocked Qn = Qn1, Q0 = DS
H = HIGH voltage level.
L = LOW voltage level.
X = don’t care.
= positive-going transition.
Fig 7.
74HC_HCT597
Timing diagram
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 15 April 2014
5 of 23
