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74HCT652D

Bus Transceivers OCTAL XCVR/REG 3-S

器件类别：逻辑    逻辑   

厂商名称：NXP(恩智浦)

厂商官网：https://www.nxp.com

器件标准：

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
SOIC
包装说明
SOP, SOP24,.4
针数
24
Reach Compliance Code
compliant
其他特性
WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型
INDEPENDENT CONTROL
计数方向
BIDIRECTIONAL
系列
HCT
JESD-30 代码
R-PDSO-G24
JESD-609代码
e4
长度
15.4 mm
负载电容（CL）
50 pF
逻辑集成电路类型
REGISTERED BUS TRANSCEIVER
最大I（ol）
0.006 A
湿度敏感等级
1
位数
8
功能数量
1
端口数量
2
端子数量
24
最高工作温度
125 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装等效代码
SOP24,.4
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度（摄氏度）
260
电源
5 V
Prop。Delay @ Nom-Sup
41 ns
传播延迟（tpd）
59 ns
认证状态
Not Qualified
座面最大高度
2.65 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
AUTOMOTIVE
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
翻译
N/A
触发器类型
POSITIVE EDGE
宽度
7.5 mm
Base Number Matches
1
文档预览
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT652
Octal bus transceiver/register;
3-state
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
FEATURES
•
Multiplexed real-time and stored
data
•
Independent register for A and B
buses
•
Independent enables for A and B
buses
•
3-state
•
Output capability: Bus driver
•
Low power consumption by CMOS
technology
•
I
CC
category: MSI.
APPLICATIONS
•
Bus interfaces.
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CP
AB
or
CP
BA
) regardless of the select pins
(S
AB
and S
BA
) or output enable (OE
AB
and OE
BA
) control pins. Depending
on the select inputs S
AB
and S
BA
data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OE
AB
and OE
BA
determine the operation mode of the
transceiver. When OE
AB
is LOW, no
data transmission from A
n
to B
n
is
74HC/HCT652
possible and when OE
BA
is HIGH,
there is no data transmission from B
n
to A
n
possible. When S
AB
and S
BA
are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OE
AB
and
OE
BA
. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
= 6 ns; V
CC
= 4.5 V; C
L
= 50 pF.
TYPICAL
SYMBOL
t
PLH
/t
PZL
PARAMETER
propagation delay A
n
/B
n
to B
n
/A
n
propagation delay CP
AB
/CP
BA
to B
n
/A
n
propagation delay S
AB
/S
BA
to B
n
/A
n
t
PHZ
/t
PZL
t
PHZ
/t
PLZ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
∑
(C
L
×
V
CC2
×
f
o
) = sum of the outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
September 1993
2
3-state output enable time OE
AB
/OE
BA
to B
n
/A
n
3-state output disable time OE
AB
/OE
BA
to B
n
/A
n
maximum clock frequency
input capacitance
power dissipation capacitance per channel
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V
13
18
20
14
12
92
3.5
26
HCT
13
20
23
15
13
92
3.5
28
ns
ns
ns
ns
ns
MHz
pF
pF
UNIT
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
ORDERING AND PACKAGE INFORMATION
PACKAGE
TYPE NUMBER
PINS
74HC/HCT652N
74HC/HCT652D
PINNING
SYMBOL
CP
AB
S
AB
OE
AB
A
0
..A
7
GND
B
7
..B
0
OE
BA
S
BA
CP
BA
V
CC
PIN
1
2
3
4..11
12
13..20
21
22
23
24
DESCRIPTION
A to B clock input
select A to B source input
output enable A to B input
A data inputs/outputs
ground (0 V)
B data inputs/outputs
output enable B to A input
select B to A source input
B to A clock input
positive supply voltage
24
24
DIL
SO
PIN POSITION
plastic
plastic
MATERIAL
74HC/HCT652
CODE
SOT101L
SOT137A
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
FUNCTION TABLE
INPUTS
(1)
OE
AB
L
L
X
H
L
L
L
L
H
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH transition
OE
BA
H
H
H
H
X
L
L
L
H
H
L
CP
AB
↑
↑
↑
H or L
↑
X
X
X
H or L
CP
BA
↑
H or L
↑
↑
↑
X
H or L
X
X
S
AB
X
X
X
L
X
X
X
X
L
H
H
S
BA
X
X
X
X
X
L
L
H
X
X
H
DATA I/O
(2)
A
1
THRU A
8
Input
Input
Input
Not specified
Ouput
Ouput
Input
Output
B
1
THRU B
8
Input
Not specified
Output
Input
Input
Input
Output
Output
Isolation
74HC/HCT652
OPERATION OR FUNCTION
HC/HCT652
Store A and B data
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
H or L H or L
H or L H or L
2. The data output functions may be enabled or disabled by various signals at OE
AB
and OE
BA
inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
Fig.4 Functional diagram.
September 1993
4
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT652
Fig.5 Logic diagram.
September 1993
5
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参数对比
与74HCT652D相近的元器件有：74HC652DB-T、74HC652PW-T、74HC652PW、74HC652DB、74HCT652N、74HC652D-T、74HCT652D-T、74HC652N。描述及对比如下：
型号 74HCT652D 74HC652DB-T 74HC652PW-T 74HC652PW 74HC652DB 74HCT652N 74HC652D-T 74HCT652D-T 74HC652N
描述 Bus Transceivers OCTAL XCVR/REG 3-S Bus Transceivers OCTAL XCVR/REG STOR 3-STATE Bus Transceivers OCTAL XCVR/REG STOR 3-STATE Bus Transceivers OCTAL XCVR/REG STOR 3-STATE Bus Transceivers OCTAL XCVR/REG STOR 3-STATE Bus Transceivers OCTAL XCVR/REG 3-S Bus Transceivers OCTAL XCVR/REG STOR 3-STATE Bus Transceivers OCTAL XCVR/REG 3-S Bus Transceivers OCTAL XCVR/REG STOR 3-STATE
是否Rohs认证 符合 符合 符合 符合 符合 符合 符合 符合 符合
零件包装代码 SOIC SSOP SOIC SOIC SSOP DIP SOIC SOIC DIP
包装说明 SOP, SOP24,.4 PLASTIC, SSOP-24 SOT-355, 24 PIN SOT-355, 24 PIN PLASTIC, SSOP-24 DIP, DIP24,.6 PLASTIC, SO-24 SOP, DIP, DIP24,.6
针数 24 24 24 24 24 24 24 24 24
Reach Compliance Code compliant unknown unknown unknown unknown unknown unknown compliant unknown
其他特性 WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列 HCT HC/UH HC/UH HC/UH HC/UH HCT HC/UH HCT HC/UH
JESD-30 代码 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDIP-T24 R-PDSO-G24 R-PDSO-G24 R-PDIP-T24
JESD-609代码 e4 e4 e4 e4 e4 e2 e4 e4 e2
长度 15.4 mm 8.2 mm 7.8 mm 7.8 mm 8.2 mm 31.7 mm 15.4 mm 15.4 mm 31.7 mm
逻辑集成电路类型 REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
位数 8 8 8 8 8 8 8 8 8
功能数量 1 1 1 1 1 1 1 1 1
端口数量 2 2 2 2 2 2 2 2 2
端子数量 24 24 24 24 24 24 24 24 24
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SOP SSOP TSSOP TSSOP SSOP DIP SOP SOP DIP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH IN-LINE SMALL OUTLINE SMALL OUTLINE IN-LINE
峰值回流温度（摄氏度） 260 260 260 260 260 NOT SPECIFIED 260 260 NOT SPECIFIED
传播延迟（tpd） 59 ns 57 ns 57 ns 57 ns 57 ns 59 ns 57 ns 59 ns 57 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 2.65 mm 2 mm 1.1 mm 1.1 mm 2 mm 5.1 mm 2.65 mm 2.65 mm 5.1 mm
最大供电电压 (Vsup) 5.5 V 6 V 6 V 6 V 6 V 5.5 V 6 V 5.5 V 6 V
最小供电电压 (Vsup) 4.5 V 2 V 2 V 2 V 2 V 4.5 V 2 V 4.5 V 2 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES YES YES YES NO YES YES NO
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD Tin/Silver (Sn/Ag) NICKEL PALLADIUM GOLD Nickel/Palladium/Gold (Ni/Pd/Au) Tin/Silver (Sn/Ag)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING THROUGH-HOLE GULL WING GULL WING THROUGH-HOLE
端子节距 1.27 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 2.54 mm 1.27 mm 1.27 mm 2.54 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 30 30 30 30 NOT SPECIFIED 30 30 NOT SPECIFIED
宽度 7.5 mm 5.3 mm 4.4 mm 4.4 mm 5.3 mm 15.24 mm 7.5 mm 7.5 mm 15.24 mm
Base Number Matches 1 1 1 1 1 1 1 1 1
是否无铅 不含铅 - - 不含铅 不含铅 不含铅 - - 不含铅
负载电容（CL） 50 pF - - - - 50 pF 50 pF 50 pF 50 pF
湿度敏感等级 1 1 1 1 1 - 1 1 -
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器件捷径:
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ
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