74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 4 — 27 August 2012
Product data sheet
1. General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC74: CMOS level
For 74HCT74: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC74N
74HCT74N
74HC74D
74HCT74D
74HC74DB
74HCT74DB
40 C
to +125
C
SSOP14
40 C
to +125
C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT108-1
SOT337-1
40 C
to +125
C
Name
DIP14
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
Type number
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 1.
Ordering information
…continued
Package
Temperature range
Name
TSSOP14
DHVQFN14
Description
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT402-1
40 C
to +125
C
40 C
to +125
C
Type number
74HC74PW
74HCT74PW
74HC74BQ
74HCT74BQ
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1SD
SD
D
CP
FF
Q
4 10
1SD 2SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
SD
Q
1Q
2Q
5
9
4
3
2
1
S
C1
1D
R
12
S
C1
1D
R
mna419
4
2
3
1D
1CP
Q
1Q
5
1Q
6
RD
5
1
6
10
1RD
2SD
SD
D
CP
FF
8
RD
13
2RD
mna420
2D
2CP
FF
Q
10
1Q
2Q
6
8
11
12
13
mna418
Q
2Q
9
9
11
RD
1RD 2RD
1 13
Q
2Q
8
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 4.
Logic diagram for one flip-flop
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
2 of 21
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
+&
+&7
5'
*1'
4
*1'
+&
+&7
5'
'
&3
6'
4
4
*1'
DDD
WHUPLQDO
LQGH[ DUHD
'
9
&&
5'
'
&3
6'
4
9
&&
5'
'
&3
6'
4
4
&3
6'
4
4
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 5.
Pin configuration for DIP14, SO14 and (T)SSOP14
Fig 6.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
complement output
ground (0 V)
complement output
output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
3 of 21
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
6. Functional description
Table 3.
Input
nSD
L
H
L
[1]
Function table
[1]
Output
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
nQ
L
H
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 4.
Input
nSD
H
H
[1]
Function table
[1]
Output
nRD
H
H
nCP
nD
L
H
nQ
n+1
L
H
nQ
n+1
H
L
H = HIGH voltage level; L = LOW voltage level;
= LOW-to-HIGH transition; Q
n+1
= state after the next LOW-to-HIGH CP transition;
X = don’t care.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14, (T)SSOP14 and DHVQFN14
packages
[1]
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
[1]
[1]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
100
65
-
-
Max
+7
20
20
25
+100
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
4 of 21
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
74HC74
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
40
-
-
-
74HCT74
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC74
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
74HCT74
V
IH
V
IL
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
V
V
input leakage
current
supply current
input
capacitance
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
0.15
0.16
-
-
3.5
0.33
0.33
1.0
40
-
-
-
-
0.4
0.4
1.0
80
V
V
A
A
pF
3.84
5.34
4.32
5.81
-
-
3.7
5.2
-
-
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
T
amb
=
40 C
to +85
C
Min
Typ
[1]
Max
T
amb
=
40 C
to +125
C
Min
Max
Unit
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
5 of 21
嵌入式系统
