DM74LS125A Quad 3-STATE Buffer
August 1986
Revised March 2000
DM74LS125A
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-imped-
ance state to the bus line. Thus the output will act neither
as a significant load nor as a driver. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Ordering Code:
Order Number
DM74LS125AM
DM74LS125ASJ
DM74LS125AN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
=
A
Inputs
A
L
H
X
C
L
L
H
Output
Y
L
H
Hi-Z
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
Hi-Z
=
3-STATE (Outputs are disabled)
© 2000 Fairchild Semiconductor Corporation
DS006387
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DM74LS125A
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
0
Parameter
Min
4.75
2
0.8
−2.6
24
70
Nom
5
Max
5.25
Units
V
V
V
mA
mA
°C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Off-State Output Current with
HIGH Level Output Voltage Applied
Off-State Output Current with
LOW Level Output Voltage Applied
Short Circuit Output Current
Supply Current
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max
I
OL
=
12 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
V
CC
=
Max, V
I
=
2.7V
V
CC
=
Max, V
I
=
0.4V
V
CC
=
Max, V
O
=
2.4V
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
O
=
0.4V
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max (Note 3)
V
CC
=
Max (Note 4)
−20
11
2.4
3.4
0.35
0.25
0.5
0.4
0.1
20
−0.4
20
−20
−100
20
mA
µA
mA
µA
µA
mA
mA
Min
Typ
(Note 2)
Max
−1.5
Units
V
V
V
Note 2:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 3:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4:
I
CC
is measured with the data control (C) inputs at 4.5V and the data inputs grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
R
L
=
667Ω
Symbol
Parameter
C
L
=
50 pF
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay Time LOW-to-HIGH Level Output
Propagation Delay Time HIGH-to-LOW Level Output
Output Enable Time to HIGH Level Output
Output Enable Time to LOW Level Output
Output Disable Time from HIGH Level Output (Note 5)
Output Disable Time from LOW Level Output (Note 5)
Max
15
18
25
25
20
20
C
L
=
150 pF
Min
Max
21
22
35
40
ns
ns
ns
ns
ns
ns
Units
Note 5:
C
L
=
5pF.
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2
DM74LS125A
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
3
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DM74LS125A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
4
DM74LS125A Quad 3-STATE Buffer
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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