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74LV4020DB,118

IC 14STAGE BINARY RIPPLE 16SSOP

器件类别：逻辑    逻辑   

厂商名称：NXP(恩智浦)

厂商官网：https://www.nxp.com

器件标准：

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器件参数
参数名称
属性值
Brand Name
NXP Semiconductor
是否Rohs认证
符合
厂商名称
NXP(恩智浦)
零件包装代码
SSOP1
包装说明
SSOP,
针数
16
制造商包装代码
SOT338-1
Reach Compliance Code
unknown
其他特性
OUTPUTS FROM 12 STAGES AVAILABLE
计数方向
UP
系列
LV/LV-A/LVX/H
JESD-30 代码
R-PDSO-G16
JESD-609代码
e4
长度
6.2 mm
负载电容（CL）
50 pF
负载/预设输入
YES
逻辑集成电路类型
BINARY COUNTER
工作模式
ASYNCHRONOUS
湿度敏感等级
1
位数
14
功能数量
1
端子数量
16
最高工作温度
125 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
SSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）
260
传播延迟（tpd）
54 ns
认证状态
Not Qualified
座面最大高度
2 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
1 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
AUTOMOTIVE
端子面层
NICKEL PALLADIUM GOLD
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
触发器类型
NEGATIVE EDGE
宽度
5.3 mm
最小 fmax
36 MHz
Base Number Matches
1
文档预览
74LV4020
14-stage binary ripple counter
Rev. 01 — 29 November 2005
Product data sheet
1. General description
The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC4020 and 74HCT4020.
The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and
Q3 to Q13).
The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all
counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
s
Optimized for low-voltage applications: 1.0 V to 5.5 V
s
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
s
Typical LOW-level output voltage (peak) or output ground bounce: V
OL(p)
< 0.8 V at
V
CC
= 3.3 V and T
amb
= 25
°C
s
Typical HIGH-level output voltage (valley) or output V
OH
undershoot: V
OH(v)
> 2 V at
V
CC
= 3.3 V and T
amb
= 25
°C
s
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
3. Applications
s
Frequency dividing circuits
s
Time delay circuits
s
Control counters
Philips Semiconductors
74LV4020
14-stage binary ripple counter
4. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns.
Symbol Parameter
t
PHL
,
t
PLH
propagation delay
CP to Q0
Qn to Q(n+1)
t
PHL
f
max
C
i
C
PD
[1]
Conditions
C
L
= 15 pF; V
CC
= 3.3 V
Min
-
-
Typ
12
7
16
100
3.5
20
Max
-
-
-
-
-
-
Unit
ns
ns
ns
MHz
pF
pF
propagation delay
MR to Qn
maximum input clock
frequency
input capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 3.3 V
-
C
L
= 15 pF; V
CC
= 3.3 V
-
-
per gate; V
I
= GND to
V
CC
[1]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
5. Ordering information
Table 2:
Ordering information
Package
Temperature range
74LV4020N
74LV4020D
74LV4020DB
74LV4020PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
Type number
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
2 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
6. Functional diagram
CP
MR
10
11
T
14-STAGE COUNTER
C
D
9
7
5
4
6
13
12
14
15
1
2
3
Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
001aad722
Fig 1. Functional diagram
CTR14
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
9
7
5
4
6
13
12
14
15
1
2
3
10
11
+
CT
0
9
7
5
4
6
13
12
14
15
1
2
3
10
CP
CT
11
MR
13
001aad723
001aad724
Fig 2. Logic symbol
Fig 3. IEC logic symbol
CP
FF
T 0
Q
FF
T 1
Q
FF
T 2
Q
FF
T 3
Q
FF
T 4
Q
FF
T 5
Q
FF
T 6
Q
Q
RD
MR
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q0
Q3
Q4
Q5
Q6
FF
T 7
Q
FF
T 8
Q
FF
T 9
Q
FF
T 10
Q
FF
T 11
Q
FF
T 12
Q
FF
T 13
Q
Q
RD
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aad725
Fig 4. Logic diagram
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
3 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
7. Pinning information
7.1 Pinning
Q11
Q12
Q13
Q5
Q4
Q6
Q3
GND
1
2
3
4
16 V
CC
15 Q10
14 Q9
13 Q7
4020
5
6
7
8
001aad721
12 Q8
11 MR
10 CP
9
Q0
Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16
7.2 Pin description
Table 3:
Symbol
Q11
Q12
Q13
Q5
Q4
Q6
Q3
GND
Q0
CP
MR
Q8
Q7
Q9
Q10
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel output 11
parallel output 12
parallel output 13
parallel output 5
parallel output 4
parallel output 6
parallel output 3
ground (0 V)
parallel output 0
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
parallel output 8
parallel output 7
parallel output 9
parallel output 10
supply voltage
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
4 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
8. Functional description
8.1 Function table
Table 4:
Input
CP
↑
↓
X
[1]
Function table
[1]
Output
MR
L
L
H
Q0, Q3 to Q13
no change
count
L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH clock transition;
↓
= HIGH-to-LOW clock transition.
8.1.1 Timing diagram
1
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aad726
2
4
8
16
32
64
128
256
512 1024 2048 4096 8192 16384
Fig 6. Timing diagram
74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
5 of 20
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参数对比
与74LV4020DB,118相近的元器件有：74LV4020PW,118、74LV4020PW,112、74LV4020D,118、74LV4020D,112、74LV4020N,112、74LV4020DB,112、935202730112、935202730118。描述及对比如下：
型号 74LV4020DB,118 74LV4020PW,118 74LV4020PW,112 74LV4020D,118 74LV4020D,112 74LV4020N,112 74LV4020DB,112 935202730112 935202730118
描述 IC 14STAGE BINARY RIPPLE 16SSOP IC 14STAGE BINARY RIPPLE 16TSSOP IC 14BIT BINARY RIPPLE 16-TSSOP IC 14STAGE BINARY RIPPLE 16SOIC IC 14BIT BINARY RIPPLE 16-SOIC IC 14BIT BINARY RIPPLE 16-DIP IC 14BIT BINARY RIPPLE 16-SSOP LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403, SSOP-16 LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403, SSOP-16
厂商名称 NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
包装说明 SSOP, TSSOP, TSSOP16,.25 TSSOP, TSSOP16,.25 SOP, SOP16,.25 SOP, SOP16,.25 DIP, DIP16,.3 SSOP, SSOP16,.3 TSSOP, TSSOP,
Reach Compliance Code unknown compliant compliant compliant compliant compliant compliant unknown unknown
Brand Name NXP Semiconductor NXP Semiconductor NXP Semiconductor NXP Semiconductor NXP Semiconductor NXP Semiconductor NXP Semiconductor - -
是否Rohs认证 符合 符合 符合 符合 符合 符合 符合 - -
零件包装代码 SSOP1 TSSOP TSSOP SOP SOP DIP SSOP1 - -
针数 16 16 16 16 16 16 16 - -
制造商包装代码 SOT338-1 SOT403-1 SOT403-1 SOT109-1 SOT109-1 SOT38-4 SOT338-1 - -
其他特性 OUTPUTS FROM 12 STAGES AVAILABLE - OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE OUTPUTS FROM 12 STAGES AVAILABLE
计数方向 UP - UP UP UP UP UP UP UP
系列 LV/LV-A/LVX/H - LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 代码 R-PDSO-G16 - R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDIP-T16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609代码 e4 - e4 e4 e4 e4 e4 - -
长度 6.2 mm - 5 mm 9.9 mm 9.9 mm 19.025 mm 6.2 mm 5 mm 5 mm
负载电容（CL） 50 pF - 50 pF 50 pF 50 pF 50 pF 50 pF - -
负载/预设输入 YES - NO NO NO NO NO YES YES
逻辑集成电路类型 BINARY COUNTER - BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER
工作模式 ASYNCHRONOUS - ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
湿度敏感等级 1 - 1 1 1 - 1 - -
位数 14 - 14 14 14 14 14 14 14
功能数量 1 - 1 1 1 1 1 1 1
端子数量 16 - 16 16 16 16 16 16 16
最高工作温度 125 °C - 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -40 °C - -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SSOP - TSSOP SOP SOP DIP SSOP TSSOP TSSOP
封装形状 RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, SHRINK PITCH - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE IN-LINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度） 260 - 260 260 260 NOT SPECIFIED 260 - -
传播延迟（tpd） 54 ns - 54 ns 54 ns 54 ns 54 ns 54 ns 54 ns 54 ns
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified - -
座面最大高度 2 mm - 1.1 mm 1.75 mm 1.75 mm 4.2 mm 2 mm 1.1 mm 1.1 mm
最大供电电压 (Vsup) 5.5 V - 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 1 V - 1 V 1 V 1 V 1 V 1 V 1 V 1 V
标称供电电压 (Vsup) 3.3 V - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES - YES YES YES NO YES YES YES
技术 CMOS - CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 AUTOMOTIVE - AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子面层 NICKEL PALLADIUM GOLD - Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) - -
端子形式 GULL WING - GULL WING GULL WING GULL WING THROUGH-HOLE GULL WING GULL WING GULL WING
端子节距 0.65 mm - 0.65 mm 1.27 mm 1.27 mm 2.54 mm 0.65 mm 0.65 mm 0.65 mm
端子位置 DUAL - DUAL DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 - 30 30 30 NOT SPECIFIED 30 - -
触发器类型 NEGATIVE EDGE - NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
宽度 5.3 mm - 4.4 mm 3.9 mm 3.9 mm 7.62 mm 5.3 mm 4.4 mm 4.4 mm
最小 fmax 36 MHz - 36 MHz 36 MHz 36 MHz 36 MHz 36 MHz 36 MHz 36 MHz
Base Number Matches 1 1 1 1 1 1 1 - -
最大频率@ Nom-Sup - - 20000000 Hz 20000000 Hz 20000000 Hz 20000000 Hz 20000000 Hz - -
最大I（ol） - - 0.006 A 0.006 A 0.006 A 0.006 A 0.006 A - -
封装等效代码 - - TSSOP16,.25 SOP16,.25 SOP16,.25 DIP16,.3 SSOP16,.3 - -
电源 - - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V - -
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器件捷径:
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ
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