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74LVT08PW,112

IC GATE AND 4CH 2-INP 14TSSOP

器件类别:逻辑    逻辑   

厂商名称:Nexperia

厂商官网:https://www.nexperia.com

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器件参数
参数名称
属性值
Brand Name
Nexperia
厂商名称
Nexperia
零件包装代码
TSSOP
包装说明
TSSOP,
针数
14
制造商包装代码
SOT402-1
Reach Compliance Code
compliant
Samacsys Description
74LVT08 - 3.3 V Quad 2-input AND gate@en-us
系列
LVT
JESD-30 代码
R-PDSO-G14
JESD-609代码
e4
长度
5 mm
逻辑集成电路类型
AND GATE
湿度敏感等级
1
功能数量
4
输入次数
2
端子数量
14
最高工作温度
85 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)
260
传播延迟(tpd)
4.8 ns
座面最大高度
1.1 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
2.7 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
BICMOS
温度等级
INDUSTRIAL
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
宽度
4.4 mm
文档预览
74LVT08
3.3 V Quad 2-input AND gate
Rev. 3 — 22 March 2017
Product data sheet
1
General description
The 74LVT08 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
The 74LVT08 is a quad 2-input AND gate.
2
Features and benefits
Wide supply voltage range from 2.7 V to 3.6 V
Output capability: +64 mA and -32 mA
TTL input and output switching levels
Latch-up protection
JESD78 Class II exceeds 500 mA
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to 85 °C
3
Ordering information
Package
Temperature
range
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
Table 1. Ordering information
Type
number
74LVT08D
74LVT08DB
74LVT08PW
Name
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Nexperia
3.3 V Quad 2-input AND gate
74LVT08
4
Functional diagram
1
2
&
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
4
1Y
2Y
3Y
4Y
mna222
3
6
8
11
&
5
6
9
10
&
8
A
12
13
&
11
B
Y
mna221
mna223
Figure 1. Logic symbol
Figure 2. IEC logic symbol
Figure 3. Logic diagram (one gate)
5
Pinning information
5.1 Pinning
74LVT08
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
aaa-026559
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
74LVT08
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
aaa-026560
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
Figure 4. Pin configuration for SOT108-1 (SO14)
Figure 5. Pin configuration for SOT337-1 and SOT402-1
(SSOP14 and TSSOP14)
5.2 Pin description
Table 2. Pin description
Symbol
1Y to 4Y
1A to 4A
1B to 4B
GND
V
CC
Pin
3, 6, 8, 11
1, 4, 9, 12
2, 5, 10, 13
7
14
Description
data output
data input
data input
ground (0 V)
supply voltage
74LVT08
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 22 March 2017
2 / 13
Nexperia
3.3 V Quad 2-input AND gate
74LVT08
6
Functional description
[1]
Table 3. Function table
Input
nA
H
H
L
L
[1]
H = HIGH voltage level; L = LOW voltage level
Output
nB
H
L
H
L
nY
H
L
L
L
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
Conditions
[1]
Min
-0.5
-0.5
-0.5
-50
-50
-
-32
-65
[2]
[1]
Max
+4.6
+7.0
+7.0
-
-
64
-
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
T
stg
T
j
P
tot
[1]
[2]
[3]
storage temperature
junction temperature
total power dissipation
T
amb
= -40 to +85 °C
[3]
-
-
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which
are detrimental to reliability.
For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
8
Recommended operating conditions
Conditions
Min
2.7
0
-20
-
All information provided in this document is subject to legal disclaimers.
Table 5. Operating conditions
Symbol Parameter
V
CC
V
I
I
OH
I
OL
74LVT08
Typ
-
-
-
-
Max
3.6
5.5
-
32
Unit
V
V
mA
mA
supply voltage
input voltage
HIGH-level output current
LOW-level output current
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 22 March 2017
3 / 13
Nexperia
3.3 V Quad 2-input AND gate
Symbol Parameter
T
amb
Δt/ΔV
ambient temperature
input transition rise and fall rate
74LVT08
Max
+85
10
Conditions
in free-air
outputs enabled
Min
-40
-
Typ
-
-
Unit
°C
ns/V
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= -40 °C to +85 °C
V
IK
V
IH
V
IL
V
OH
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output
voltage
Conditions
V
CC
= 2.7 V; I
IK
= -18 mA
Min
-1.2
2.0
-
Typ
[1]
Max
-
Unit
V
V
V
V
V
V
V
V
V
μA
μA
μA
-
-
-
0.8
-
V
CC
= 2.7 V to 3.6 V; I
OH
= -100 μA
V
CC
= 2.7 V; I
OH
= -6 mA
V
CC
= 3.0 V; I
OH
= -20 mA
V
CC
- 0.2
2.4
2.0
-
-
-
-
-
-
-
-
-
-
0.2
0.5
0.5
10
±1
±100
V
OL
LOW-level output voltage V
CC
= 2.7 V; I
OL
= 100 μA
V
CC
= 2.7 V; I
OL
= 24 mA
V
CC
= 3.0 V; I
OL
= 32 mA
I
I
input leakage current
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
V
CC
= 3.6 V; V
I
= V
CC
or GND
I
OFF
I
CC
power-off leakage
current
supply current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
V
CC
= 3.6 V; V
I
= GND or V
CC
; I
O
= 0 A
output HIGH
output LOW
[2]
-
-
-
-
1
0.02
2
0.2
mA
mA
μA
ΔI
CC
additional supply current
per input pin; V
CC
= 3.0 V to 3.6 V;
one input at V
CC
- 0.6 V
and other inputs at V
CC
or GND
V
I
= 0 V or 3.0 V
V
O
= 0 V or 3.0 V
C
I
C
O
[1]
[2]
input capacitance
output capacitance
-
-
4
10
-
-
pF
pF
Typical values are measured at T
amb
= 25 °C and V
CC
= 3.3 V.
This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
74LVT08
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 22 March 2017
4 / 13
Nexperia
3.3 V Quad 2-input AND gate
74LVT08
10 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 7.
Symbol Parameter
T
amb
= -40 °C to +85 °C
t
PLH
LOW to HIGH
propagation delay
Conditions
nA or nB to nY; see
Figure 6
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
Min
Typ
[1]
Max
Unit
-
1
-
3.0
4.7
3.9
ns
ns
t
PHL
HIGH to LOW
propagation delay
nA or nB to nY; see
Figure 6
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
-
1
-
3.4
4.8
4.6
ns
ns
[1]
Typical values are measured at V
CC
= 3.3 V and T
amb
= 25 °C.
10.1 Waveforms and test circuit
V
I
nA, nB input
GND
t
PHL
V
OH
nY output
V
OL
V
M
mna224
V
M
t
PLH
Measurement points are given in
Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Figure 6. Propagation delay input (nA, nB) to output (nY)
Table 8. Measurement points
Input
V
M
1.5 V
Output
V
I
2.7 V
V
M
1.5 V
74LVT08
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 22 March 2017
5 / 13
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参数对比
与74LVT08PW,112相近的元器件有:74LVT08DB,118、74LVT08DB,112、74LVT08PW,118、74LVT08D,118、74LVT08D,112。描述及对比如下:
型号 74LVT08PW,112 74LVT08DB,118 74LVT08DB,112 74LVT08PW,118 74LVT08D,118 74LVT08D,112
描述 IC GATE AND 4CH 2-INP 14TSSOP IC GATE AND 4CH 2-INP 14SSOP IC GATE AND 4CH 2-INP 14SSOP IC GATE AND 4CH 2-INP 14TSSOP IC GATE AND 4CH 2-INP 14SO IC GATE AND 4CH 2-INP 14SO
Brand Name Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
厂商名称 Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
零件包装代码 TSSOP SSOP1 SSOP1 TSSOP SOIC SOIC
包装说明 TSSOP, SSOP, SSOP, TSSOP, SOP, SOP,
针数 14 14 14 14 14 14
制造商包装代码 SOT402-1 SOT337-1 SOT337-1 SOT402-1 SOT108-1 SOT108-1
Reach Compliance Code compliant compliant compliant compliant compliant compliant
Samacsys Description 74LVT08 - 3.3 V Quad 2-input AND gate@en-us 74LVT08 - 3.3 V Quad 2-input AND gate@en-us 74LVT08 - 3.3 V Quad 2-input AND gate@en-us 74LVT08 - 3.3 V Quad 2-input AND gate@en-us 74LVT08 - 3.3 V Quad 2-input AND gate@en-us 74LVT08 - 3.3 V Quad 2-input AND gate@en-us
系列 LVT LVT LVT LVT LVT LVT
JESD-30 代码 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609代码 e4 e4 e4 e4 e4 e4
长度 5 mm 6.2 mm 6.2 mm 5 mm 8.65 mm 8.65 mm
逻辑集成电路类型 AND GATE AND GATE AND GATE AND GATE AND GATE AND GATE
湿度敏感等级 1 1 1 1 1 1
功能数量 4 4 4 4 4 4
输入次数 2 2 2 2 2 2
端子数量 14 14 14 14 14 14
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP SSOP SSOP TSSOP SOP SOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE
传播延迟(tpd) 4.8 ns 4.8 ns 4.8 ns 4.8 ns 4.8 ns 4.8 ns
座面最大高度 1.1 mm 2 mm 2 mm 1.1 mm 1.75 mm 1.75 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES
技术 BICMOS BICMOS BICMOS BICMOS BICMOS BICMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.65 mm 0.65 mm 0.65 mm 0.65 mm 1.27 mm 1.27 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL
宽度 4.4 mm 5.3 mm 5.3 mm 4.4 mm 3.9 mm 3.9 mm
峰值回流温度(摄氏度) 260 260 260 - 260 260
处于峰值回流温度下的最长时间 30 30 30 - 30 30
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