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74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

Rev. 04 — 19 May 2006

Product data sheet

1. General description

The 74LVT16501A is a high-performance BiCMOS product designed for V

operation at

3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions.

Data ﬂow in each direction is controlled by output enable (OEAB and OEBA), latch enable

(LEAB and LEBA), and clock (CPAB and CPBA) inputs.

For A-to-B data ﬂow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.

If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on the LOW-to-HIGH

transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the

outputs are in the high-impedance state.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).

Active bus hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

2. Features

18-bit bidirectional bus interface

3-state buffers

Output capability: +64 mA to

−32

TTL input and output switching levels

Input and output interface capability to systems at 5 V supply

Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

Live insertion and extraction permitted

Power-up reset

Power-up 3-state

No bus current loading when output is tied to 5 V bus

Positive-edge triggered clock inputs

Latch-up protection:

JESD78: exceeds 500 mA

ESD protection:

MIL STD 883, method 3015: exceeds 2000 V

Machine model: exceeds 200 V

Philips Semiconductors

74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

3. Quick reference data

Table 1.

Quick reference data

GND = 0 V; T

amb

= 25

Symbol Parameter

PLH

PHL

propagation delay An to Bn or

Bn to An

propagation delay An to Bn or

Bn to An

input capacitance (control pins)

input/output capacitance

(I/O pins)

quiescent supply current

Conditions

= 50 pF;

= 3.3 V

= 50 pF;

= 3.3 V

= 0 V or 3.0 V

outputs disabled;

I/O

= 0 V or 3.0 V

outputs disabled;

= 3.6 V

Min

Typ

1.9

Max

Unit

µA

4. Ordering information

Table 2.

Ordering information

Package

Temperature range Name

74LVT16501ADL

−40 °C

to +85

°C

SSOP56

TSSOP56

Description

plastic shrink small outline package; 56 leads;

body width 7.5 mm

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

Version

SOT371-1

SOT364-1

Type number

74LVT16501ADGG

−40 °C

to +85

°C

74LVT16501A_4

Product data sheet

Rev. 04 — 19 May 2006

2 of 19

Philips Semiconductors

74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

5. Functional diagram

OEAB

CPAB

LEAB

30 28 27 55 2

LEBA

OEBA

LEAB

CPBA

CPAB

OEAB

OEBA

CPBA

LEBA

B10

B11

B12

B13

B14

B15

B16

B17

A10

A11

A12

A13

A14

A15

A16

A17

EN1

2C3

EN4

5C6

B10

B11

B12

B13

B14

B15

B16

B17

A10

A11

A12

A13

A14

A15

A16

A17

001aad339

001aad338

Fig 1. Logic symbol

Fig 2. IEC logic symbol

OEAB

CPAB

LEAB

LEBA

CPBA

OEBA

CLK

to 17 other channels

001aaf011

Fig 3. Logic diagram

74LVT16501A_4

Product data sheet

Rev. 04 — 19 May 2006

3 of 19

Philips Semiconductors

74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

6. Pinning information

6.1 Pinning

OEAB

LEAB

GND

56 GND

55 CPAB

54 B0

53 GND

52 B1

51 B2

50 V

49 B3

48 B4

47 B5

46 GND

45 B6

44 B7

43 B8

42 B9

41 B10

40 B11

39 GND

38 B12

37 B13

36 B14

35 V

34 B15

33 B16

32 GND

31 B17

30 CPBA

29 GND

001aaf010

A5 10

GND 11

A6 12

A7 13

A8 14

A9 15

A10 16

A11 17

GND 18

A12 19

A13 20

A14 21

A15 23

A16 24

GND 25

A17 26

OEBA 27

LEBA 28

74LVT16501A

Fig 4. Pin conﬁguration

6.2 Pin description

Table 3.

Symbol

OEAB

LEAB

GND

74LVT16501A_4

Pin description

Description

A-to-B output enable input

A-to-B latch enable input

data input or output A0

ground (0 V)

data input or output A1

data input or output A2

voltage supply

data input or output A3

Product data sheet

Rev. 04 — 19 May 2006

4 of 19

Philips Semiconductors

74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

Pin description

…continued

Description

data input or output A4

data input or output A5

ground (0 V)

data input or output A6

data input or output A7

data input or output A8

data input or output A9

data input or output A10

data input or output A11

ground (0 V)

data input or output A12

data input or output A13

data input or output A14

voltage supply

data input or output A15

data input or output A16

ground (0 V)

data input or output A17

B-to-A output enable input (active LOW)

B-to-A latch enable input

ground (0 V)

B-to-A clock input (active rising edge)

data input or output B17

ground (0 V)

data input or output B16

data input or output B15

voltage supply

data input or output B14

data input or output B13

data input or output B12

ground (0 V)

data input or output B11

data input or output B10

data input or output B9

data input or output B8

data input or output B7

data input or output B6

ground (0 V)

data input or output B5

data input or output B4

data input or output B3

Table 3.

Symbol

GND

A10

A11

GND

A12

A13

A14

A15

A16

GND

A17

OEBA

LEBA

GND

CPBA

B17

GND

B16

B15

B14

B13

B12

GND

B11

B10

GND

74LVT16501A_4

Product data sheet

Rev. 04 — 19 May 2006

5 of 19

参数对比

与74LVT16501ADGG-T相近的元器件有：935194800118、935203030512、74LVT16501ADGG、935194800512、935194800518、935203030112、935203030118、935203030518。描述及对比如下：

型号	74LVT16501ADGG-T	935194800118	935203030512	74LVT16501ADGG	935194800512	935194800518	935203030112	935203030118	935203030518
描述	IC LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56, Bus Driver/Transceiver	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.5 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56	IC LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56, Bus Driver/Transceiver	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.5 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.5 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56	LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56
包装说明	6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56	SSOP,	TSSOP,	6.1 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56	SSOP,	SSOP,	TSSOP,	TSSOP,	TSSOP,
Reach Compliance Code	unknown	unknow	unknown	compliant	unknow	unknow	unknow	unknow	unknow
其他特性	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
JESD-30 代码	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
JESD-609代码	e4	e4	e4	e4	e4	e4	e4	e4	e4
长度	14 mm	18.425 mm	14 mm	14 mm	18.425 mm	18.425 mm	14 mm	14 mm	14 mm
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
位数	18	18	18	18	18	18	18	18	18
功能数量	1	1	1	1	1	1	1	1	1
端口数量	2	2	2	2	2	2	2	2	2
端子数量	56	56	56	56	56	56	56	56	56
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	SSOP	TSSOP	TSSOP	SSOP	SSOP	TSSOP	TSSOP	TSSOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns
座面最大高度	1.2 mm	2.8 mm	1.2 mm	1.2 mm	2.8 mm	2.8 mm	1.2 mm	1.2 mm	1.2 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.635 mm	0.5 mm	0.5 mm	0.635 mm	0.635 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
宽度	6.1 mm	7.5 mm	6.1 mm	6.1 mm	7.5 mm	7.5 mm	6.1 mm	6.1 mm	6.1 mm
厂商名称	NXP(恩智浦)	-	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)