74VHC373 Octal D-Type Latch with 3-STATE Outputs
February 1993
Revised April 2005
74VHC373
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC373 is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is LATCHED. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
5.0 ns (typ) @ V
CC
V
NIL
5V
s
High Noise Immunity: V
NIH
s
Low Noise: V
OLP
28% V
CC
(Min)
s
Power Down Protection is provided on all inputs
0.6V (typ)
4
P
A (Max) @ T
A
25
q
C
s
Low Power Dissipation: I
CC
s
Pin and Function Compatible with 74HC373
Ordering Code:
Order Number
74VHC373M
74VHC373SJ
74VHC373MTC
74VHC373N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
© 2005 Fairchild Semiconductor Corporation
DS011555
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74VHC373
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Outputs
Truth Table
Inputs
LE
X
H
H
L
H
L
Z
X
O
0
Outputs
D
n
X
L
H
X
O
n
Z
L
H
O
0
OE
H
L
L
L
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Functional Description
The VHC373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The 3-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the
standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74VHC373
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
20 mA
r
20 mA
r
25 mA
r
75 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
V
CC
3.3V
r
0.3V
5.0
r
0.5V
0
a
100 ns/V
0
a
20 ns/V
2.0V to
5.5V
0V to
5.5V
0V to V
CC
40
q
C to
85
q
C
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
I
OL
I
OL
V
IN
V
OUT
V
IN
V
IN
V
IH
or V
IL
V
CC
or GND
5.5 or GND
V
CC
or GND
4 mA
8 mA
V
V
V
IN
V
IH
or V
IL
I
OH
I
OH
I
OL
V
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
1.50
0.7 V
CC
Units
V
Conditions
0.50
0.3 V
CC
V
V
IN
V
IH
or V
IL
I
OH
50
P
A
4 mA
8 mA
50
P
A
r
0.25
r
0.1
4.0
r
2.5
r
1.0
40.0
P
A
P
A
P
A
Noise Characteristics
Symbol
V
OLP
(Note 3)
V
OLV
(Note 3)
V
IHD
(Note 3)
V
ILD
(Note 3)
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
Typ
0.6
25
q
C
Limits
0.9
Units
V
V
V
V
C
L
C
L
C
L
C
L
Conditions
50 pF
50 pF
50 pF
50 pF
0.6
0.9
3.5
1.5
Note 3:
Parameter guaranteed by design.
3
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74VHC373
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
Time (LE to O
n
)
5.0
r
0.5
t
PLH
t
PHL
Propagation Delay
Time (D to O
n
)
5.0
r
0.5
t
PZL
t
PZH
3-STATE
Output
Enable Time
t
PLZ
t
PHZ
t
OSLH
t
OSHL
C
IN
C
OUT
C
PD
3-STATE Output
Disable Time
Output to
Output Skew
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
Note 4:
Parameter guaranteed by design. t
OSLH
|t
PLH max
t
PLH min
|; t
OSHL
|t
PHL max
t
PHL
min|
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.) C
PD
• V
CC
• f
IN
I
CC
/8 (per Latch). The total C
PD
when n pcs. of the Latch operates can be
calculated by the equation: C
PD
(total) 14
13n.
V
CC
(V)
3.3
r
0.3
Min
T
A
25
q
C
Typ
7.0
9.5
4.9
6.4
7.3
9.8
5.0
6.5
7.3
9.8
5.5
7.0
9.5
6.5
Max
11.0
14.5
7.2
9.2
11.4
14.9
7.2
9.2
11.4
14.9
8.1
10.1
13.2
9.2
1.5
1.0
4
6
27
10
T
A
40
q
C to
85
q
C
Max
13.0
16.5
8.5
10.5
13.5
17.0
8.5
10.5
13.5
17.0
9.5
11.5
15.0
10.5
1.5
1.0
10
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Min
Units
ns
ns
Conditions
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
R
L
1 k
:
C
L
C
L
C
L
C
L
R
L
1 k
:
C
L
C
L
(Note 4)
V
CC
V
CC
Open
5.0V
C
L
C
L
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
50 pF
50 pF
3.3
r
0.3
ns
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
ns
ns
ns
ns
pF
pF
pF
(Note 5)
AC Operating Requirements
Symbol
t
W
(H)
t
S
t
H
Parameter
Minimum Pulse Width (LE)
Minimum Set-Up Time
Minimum Hold Time
V
CC
(V)
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
Min
5.0
5.0
4.0
4.0
1.0
1.0
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
5.0
5.0
4.0
4.0
1.0
1.0
Min
Units
ns
ns
ns
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4
74VHC373
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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