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781401CA

DPST, 2 Func, 2 Channel, JFET, CDIP14, SIDEBRAZED, DIP-14

器件类别:模拟混合信号IC    信号电路   

厂商名称:Vishay(威世)

厂商官网:http://www.vishay.com

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器件参数
参数名称
属性值
厂商名称
Vishay(威世)
零件包装代码
DIP
包装说明
DIP,
针数
14
Reach Compliance Code
unknown
模拟集成电路 - 其他类型
DPST
JESD-30 代码
R-CDIP-T14
长度
18.54 mm
标称负供电电压 (Vsup)
-18 V
信道数量
2
功能数量
2
端子数量
14
标称断态隔离度
60 dB
最大通态电阻 (Ron)
30 Ω
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
认证状态
Not Qualified
座面最大高度
4.44 mm
标称供电电压 (Vsup)
12 V
表面贴装
NO
最长断开时间
1600 ns
最长接通时间
600 ns
技术
JFET
温度等级
MILITARY
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
宽度
7.62 mm
Base Number Matches
1
文档预览
DG129
Dual DPST JFET Analog Switch
Features
D
D
D
D
D
Standby Power: <1 mW
Bipolar Drivers
Constant r
DS(on)
Over Signal Range
Off Isolation: > 60 dB @ 1 MHz
Make-Before-Break
Benefits
D
D
D
D
D
Minimizes Standby Power Requirements
Better Radiation Tolerance
Less Distortion
Higher Frequency Switching
Smooth Closed Loop Response
Applications
D
D
D
D
Battery Powered Systems
Aerospace Control Systems
Low Distortion Circuits
High Frequency Switching
Circuits
Description
The DG129 is a dual double-pole single-throw analog
switch for use in instrumentation, control, and audio
communication systems. It is ideally suited for
applications requiring a constant on-resistance over the
entire analog range.
On-resistance for the DG129 is 20
W
(typical), and
on-leakage is < 2 nA. With all switches off, total power
consumption is < 750
mW.
These switches have
make-before-break action and due to the processing are
relatively radiation tolerant. An enable pin (V
R
)
simplifies interfacing with microprocessor, or other logic.
Each device contains four junction field-effect transistors
(JFETs) to achieve constant on-resistance. Level-shifting
drivers enable low-level inputs (0.8 to 2.5 V) to control
the on-off state of each switch. With logic “0” at the driver
input the switches will be off. With a logic “1” at the input
the switches will be on. In the on-state each switch will
conduct current in either direction, and in the off-state
each switch will block voltages up to 20 V peak-to-peak.
Functional Block Diagram and Pin Configuration
Two DPST Switches per Package
Dual-In-Line
Truth Table
Logic
Switch
OFF
ON
Logic “0”
v
0.8 V
Logic “1”
w
2.5 V
Switches Shown for Logic “1” Input
14 S
2
0
13 IN
2
12 V–
11 V+
10 V
R
(ENABLE)
9
8
IN
1
S
1
1
D
2
S
4
D
4
NC
D
3
S
3
D
1
1
2
3
4
5
6
7
Ordering Information
Temp Range
–55 to 125_C
55
Package
14-Pin
14 Pin Sidebraze
Part Number
DG129AP/883
781401CA
Top View
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70030.
Siliconix
S-44054—Rev. C, 16-Oct-95
1
Not Recommended for New Designs
DG129
Absolute Maximum Ratings
V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
V+ to V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
V
D
or V
S
to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
V
D
to V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
"22
V
V+ to V
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
R
to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
IN
to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Notes:
a. All leads welded or soldered to PC Board.
V+ to V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
IN
to V
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
"6
V
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Storage Temperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150_C
Power Dissipationa
14-Pin DIP
b
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
b.
Derate 11 mW/_C above 75_C
Specifications
a
Test Conditions
Unless Otherwise Specified
Parameter
Switch
Analog Signal Range
Drain-Source On-Resistance
Source-Off Leakage Current
Drain-Off Leakage Current
Channel-On Leakage Current
V
ANALOG
r
DS(on)
I
S
(off)
I
D
(off)
I
D(on)
I
S
= –10 mA, V
D
= 10 V
V
S
=
"10
V, V
D
=
#10
V
V
D
=
"10
V, V
S
=
#10
V
V
D
= V
S
= –10 V
Full
Room
Full
Room
Full
Room
Full
Room
Full
–1
–100
–1
–100
–2
–100
–10
20
0.03
0.02
–0.03
10
30
60
1
100
1
100
nA
V
W
A Suffix
–55 to 125_C
Symbol
V+
V = 12 V, V– = –18 V,
VV
18 V
V
R
= 0 V, V
IN
= 0.8 V or 2.5 V
f
Temp
b
Min
d
Typ
c
Max
d
Unit
Input
Input Current
with Input Voltage High
Input Current
with Input Voltage Low
I
INH
I
INL
V
IN
= 2.5 V
V
IN
= 0.8 V
Room
Full
Room
Full
15
0.005
60
120
0.1
2
mA
Dynamic
Turn-On Time
Turn-Off Time
Source-Off Capacitance
Drain-Off Capacitance
Channel-On Capacitance
Off-Isolation
t
ON
t
OFF
C
S(off)
C
D(off)
C
D(on)
OIRR
R
L
= 75
W,
f = 1 MHz
See Figure 1
f = 1 MHz
V
D
, V
S
= 0
Room
Room
Room
Room
Room
Room
0.5
1.1
2.4
2.4
2.8
> 60
dB
pF
0.6
1.6
ms
Supply
Positive Supply Current
Negative Supply Current
Reference Supply Current
Positive Supply Current
Negative Supply Current
Reference Supply Current
I+
I–
I
R
I+
I–
I
R
All Channel Off
Both V
IN
= 0 V
One Channel On
V
IN
= 2.5 V
Room
Room
Room
Room
Room
Room
–25
–25
–1.8
–1.4
2.5
–1.6
–1.1
0.6
–0.5
–0.5
25
mA
3
mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART (Section 5 of the 1994 Data Book or FaxBack number 7103).
b. Room = 25_C, Full = –55 to 125_C.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. V
IN
= input voltage to perform proper function.
2
Siliconix
S-44054—Rev. C, 16-Oct-95
Not Recommended for New Designs
DG129
Test Circuits
Switch output waveform shown for V
S
= constant with
logic input waveform as shown. Note that V
S
may be + or
– as per switching time test circuit. V
O
is the steady state
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
waveform.
+12 V
V+
–10 V
S
IN
3V
GND
V–
R
L
1 kW
C
L
35 pF
D
V
O
Logic
Input
Switch
Input
Switch
Output
3V
50%
0V
V
S
90%
0V
t
ON
–V
S
t
r
<10 ns
t
f
<10 ns
0V
–18 V
t
OFF
C
L
(includes fixture and stray capacitance)
V
O
= V
S
R
L
R
L
+ r
DS(on)
Logic “1” = Switch On
Figure 1.
Switching Time
Application Hints
V
IN
Logic Input
Voltage
V
INH(min)
/V
INL(max)
(V)
0
0
0
0
0
2.5/0.8
2.5/0.8
2.5/0.8
2.5/0.8
2.5/0.8
V+
Positive Supply Voltage
(V)
12
15
7
5
5
V–
Negative Supply
Voltage
(V)
–18
–15
–12
–15
–10
V
R
Reference
Voltage
(V)
V
S
or V
D
Analog Voltage
Range
(V)
–10 to 10
–7 to 13
–5 to 5
–7 to 3
–2 to 3
Siliconix
S-44054—Rev. C, 16-Oct-95
3
Not Recommended for New Designs
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参数对比
与781401CA相近的元器件有:781401CX。描述及对比如下:
型号 781401CA 781401CX
描述 DPST, 2 Func, 2 Channel, JFET, CDIP14, SIDEBRAZED, DIP-14 IC DBL POLE SGL THROW SWITCH, Multiplexer or Switch
厂商名称 Vishay(威世) Vishay(威世)
Reach Compliance Code unknown unknown
模拟集成电路 - 其他类型 DPST DPST
认证状态 Not Qualified Not Qualified
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