Low Voltage/Low Skew, 1:8 PCI/PCI-X
Zero Delay clock Generator
Data Sheet
87608I
G
ENERAL
D
ESCRIPTION
The 87608I has a selectable REF_CLK or crystal input. The
REF_CLK input accepts LVCMOS or LVTTL input levels.
The 87608I has a fully integrated PLL along with frequency
configurable clock and feedback outputs for multiplying and
regenerating clocks with “zero delay”.
The 87608I is a 1:8 PCI/PCI-X Clock Generator. The 87608I
has a selectable REF_CLK or crystal input. The REF_CLK input
accepts LVCMOS or LVTTL input levels. The 87608I has a fully
integrated PLL along with frequency configurable clock and
feedback outputs for multiplying and regenerating clocks with
“zero delay”. The PLL’s VCO has an operating range of 250MHz-
500MHz, allowing this device to be used in a variety of general
purpose clocking applications. For PCI/PCI-X applications in
particular, the VCO frequency should be set to 400MHz. This
can be accomplished by supplying 33.33MHz, 25MHz, 20MHz,
or 16.66MHz on the reference clock or crystal input and by
selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback
divide value. The dividers on each of the two output banks can
then be independently configured to generate 33.33MHz (÷12),
66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3).
The 87608I is characterized to operate with its core supply
at 3.3V and each bank supply at 3.3V or 2.5V. The 87608I is
packaged in a small 7x7mm body LQFP, making it ideal for use
in space-constrained applications.
F
EATURES
•
Fully integrated PLL
•
Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance
•
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
•
Maximum output frequency: 166.67MHz
•
Maximum crystal input frequency: 38MHz
•
Maximum REF_IN input frequency: 41.67MHz
•
Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
•
Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
•
VCO range: 200MHz to 500MHz
•
Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V
•
Period jitter, RMS: 20ps (maximum)
•
Output skew: 250ps (maximum)
•
Bank skew: 60ps (maximum)
•
Static phase offset: 160ps ± 160ps
•
Voltage Supply Modes:
V
DD
(core/inputs), V
DDA
(analog supply for PLL),
V
DDOA
(output bank A),
V
DDOB
(output bank B, REF_OUT, FB_OUT)
V
DD
/V
DDA
/V
DDOA
/V
DDOB
3.3/3.3/3.3/3.3
3.3/3.3/2.5/3.3
3.3/3.3/3.3/2.5
3.3/3.3/2.5/2.5
•
-40°C to 85°C ambient operating temperature
V
DDOB
P
IN
A
SSIGNMENT
XTAL_SEL
PLL_SEL
REF_IN
V
DDOA
XTAL2
XTAL1
V
DDA
•
Available in lead-free RoHS compliant package
32 31 30 29 28 27 26 25
QA0
QA1
GND
QA2
QA3
V
DDOA
MR
DIV_SELA0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DIV_SELA1
DIV_SELB0
DIV_SELB1
FBDIV_SEL0
FBDIV_SEL1
V
DD
FB_IN
GND
24
QB0
QB1
GND
QB2
QB3
V
DDOB
REF_OUT
FB_OUT
ICS87608I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
23
22
21
20
19
18
17
©2016 Integrated Device Technology, Inc
1
Revision C January 25, 2016
87608I Data Sheet
B
LOCK
D
IAGRAM
©2016 Integrated Device Technology, Inc
2
Revision C January 25, 2016
87608I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2,
4, 5
3, 16, 22
6, 32
7
8,
9,
10,
11
12,
13
14
15
17
18
19, 25
20, 21,
23, 24
26
27
28
29, 30
31
Name
QA0, QA1,
QA2, QA3
GND
V
DDOA
MR
DIV_SELA0,
DIV_SELA1,
DIV_SELB0,
DIV_SELB1
FBDIV_SEL0,
FBDIV_SEL1
V
DD
FB_IN
FB_OUT
REF_OUT
V
DDOB
QB3, QB2,
QB1, QB0
PLL_SEL
V
DDA
XTAL_SEL
XTAL1, XTAL2
REF_IN
Type
Output
Power
Power
Input
Description
Bank A clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Power supply ground.
Output supply pins for Bank A outputs.
Active HIGH Master Reset. When logic HIGH, the internal dividers
Pulldown are reset causing the outputs go low. When logic LOW, the internal divid-
ers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for clock outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divide value for reference clock output and feedback output.
LVCMOS / LVTTL interface levels.
Core supply pin.
Pulldown
Feedback input to phase detector for generating clocks with
“zero delay”. LVCMOS / LVTTL interface levels.
Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels.
Reference clock output. LVCMOS / LVTTL interface levels.
Output supply pins for Bank B and REF_OUT, FB_OUT outputs.
Bank B clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Pullup
Selects between crystal oscillator or reference clock as the PLL reference
source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW.
LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Input
Input
Power
Input
Output
Output
Power
Output
Input
Power
Input
Input
Input
Pulldown
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
V
DD
, V
DDA
, V
DDOX
= 3.465V
V
DD
, V
DDA
= 3.465V; V
DDOX
= 2.625V
15
Test Conditions
Minimum
Typical
4
51
51
9
11
Maximum
Units
pF
kΩ
kΩ
pF
pF
Ω
V
DDOX
denotes V
DDOA
and V
DDOB
.
©2016 Integrated Device Technology, Inc
3
Revision C January 25, 2016
87608I Data Sheet
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Inputs
MR
1
0
QA0:QA3
LOW
Active
Outputs
QB0:QB3, FB_OUT, REF_OUT
LOW
Active
T
ABLE
3B. O
PERATING
M
ODE
F
UNCTION
T
ABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
T
ABLE
3C. PLL I
NPUT
F
UNCTION
T
ABLE
Inputs
XTAL_SEL
0
1
PLL Input
REF_IN
XTAL Oscillator
T
ABLE
3D. C
ONTROL
F
UNCTION
T
ABLE
Inputs
FBDIV_
SEL1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FBDIV_
SEL0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bank B
Bank B
Bank A
Bank A
Outputs
PLL_SEL =1
DIV_
SELA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Fre-
quency Range
(MHz)
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
10 - 25
10 - 25
10 - 25
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
QX0:QX3
x4
x3
x2
x1
x 5.33
x4
x 2.667
x 1.33
x 6.667
x5
x 3.33
x 1.66
x8
x6
x4
x2
Frequency
QX0:QX3 (MHz)
66.68 - 166.68
50 - 125
33.34 - 83.34
16.67 - 41.67
66.63 - 166.56
50 - 125
33.34 - 83.34
16.63 - 41.56
66.67 - 166.68
50 - 125
33.30 - 83.25
16.60 - 41.50
66.64 - 166.64
50 - 125
33.32 - 83.32
16.66 - 41.66
FB_OUT
(MHz)
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
10 - 25
10 - 25
10 - 25
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
DIV_
SELB1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIV_
SELB0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIV_
SELA1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NOTE: VCO frequency range for all configurations above is 200MHz to 500MHz.
©2016 Integrated Device Technology, Inc
4
Revision C January 25, 2016
87608I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDOX
I
DD
I
DDA
I
DDOA
I
DDOB
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
185
15
20
20
Units
V
V
V
mA
mA
mA
mA
V
DDOX
denotes V
DDOA
, V
DDOB
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
Input
High Voltage
MR, DIV_ SELx0, DIV_SELx1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
REF_IN
Input
Low Voltage
MR, DIV_ SELx0, DIV_SELx1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
REF_IN
Input
High Current
DIV_ SELx0, DIV_SELx1, FB-
DIV_SEL0, FBDIV_SEL1, MR,
FB_IN
XTAL_SEL, PLL_SEL
DIV_ SELx0, DIV_SELx1, FB-
DIV_SEL0, FBDIV_SEL1, MR,
FB_IN
XTAL_SEL, PLL_SEL
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 2.625V
-5
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
V
IH
V
IL
I
IH
I
IL
Input
Low Current
-150
2.6
1.8
0.5
µA
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
DDOX
/2. See Parameter Measurement Information section,
“3.3V Output Load Test Circuit”.
©2016 Integrated Device Technology, Inc
5
Revision C January 25, 2016
