PCA9691
8-bit A/D and D/A converter
Rev. 02 — 27 January 2010
Product data sheet
1. General description
The PCA9691 is a single chip, single supply, low power, 8-bit CMOS
1
data acquisition
device with four analog inputs, one analog output and a serial I
2
C-bus interface. Three
address pins (A0, A1, and A2) are used for programming the hardware address, allowing
the use of up to 64 PCA9691 devices connected to the I
2
C-bus without additional
hardware. Address, control and data to and from the PCA9691 are transferred via the
serial two-line bidirectional I
2
C-bus.
The functions of the PCA9691 include:
•
•
•
•
Analog input multiplexing
On-chip sample and hold
8-bit Analog-to-Digital (A/D) conversion
8-bit Digital-to-Analog (D/A) conversion
The maximum conversion rate is given by the maximum frequency of the I
2
C-bus.
2. Features
8-bit successive approximation A/D conversion
Four analog inputs programmable as single-ended or differential inputs
64 different addresses by three hardware address pins
1 MHz Fast-mode Plus (Fm+) I
2
C-bus via serial input/output
Sampling rate given by I
2
C-bus frequency
Single supply voltage; operating from 2.5 V to 5.5 V
Low standby current
Analog voltage from V
SS
to V
DD
Multiplying Digital-to-Analog Converter (DAC) with one analog output
On-chip sample and hold circuit
Auto-incremented channel selection
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in
Section 14.
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
3. Ordering information
Table 1.
Ordering information
Name
PCA9691BS
PCA9691TS
PCA9691T
HVQFN16
TSSOP16
SO16
Description
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4
×
4
×
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic small outline package; 16 leads; body width
7.5 mm
Version
SOT629-1
SOT403-1
SOT162-1
Type number Package
4. Marking
Table 2.
Marking codes
Marking code
9691
PCA9691
PCA9691T
Type number
PCA9691BS
PCA9691TS
PCA9691T
5. Block diagram
SCL
SDA
A0
A1
A2
EXT
V
DD
V
SS
OSC
AIN0
AIN1
AIN2
AIN3
SAMPLE
AND
HOLD
ANALOG
MULTIPLEXER
SAMPLE
AND
HOLD
POWER-ON
RESET
OSCILLATOR
I
2
C-BUS
INTERFACE
STATUS
REGISTER
DAC DATA
REGISTER
ADC DATA
REGISTER
PCA9691
CONTROL
LOGIC
COMPARATOR
SUCCESSIVE
APPROXIMATION
REGISTER
AND
LOGIC
8
AOUT
DAC
VREF
AGND
001aag462
Fig 1.
Block diagram of PCA9691
PCA9691_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 January 2010
2 of 31
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
6. Pinning information
6.1 Pinning
13 AOUT
12 VREF
11 AGND
10 EXT
9
5
6
7
8
OSC
SCL
16 AIN1
15 AIN0
V
SS
terminal 1
index area
AIN2
AIN3
A0
A1
1
2
PCA9691BS
3
4
SDA
A2
14 V
DD
001aag523
Transparent top view
For mechanical details, see
Figure 25.
Fig 2.
Pin configuration for HVQFN16 (PCA9691BS)
AIN0
AIN1
AIN2
AIN3
A0
A1
A2
V
SS
1
2
3
4
5
6
7
8
001aag522
16 V
DD
15 AOUT
14 VREF
13 AGND
12 EXT
11 OSC
10 SCL
9
SDA
PCA9691TS
Top view. For mechanical details, see
Figure 26.
Fig 3.
Pin configuration for TSSOP16 (PCA9691TS)
AIN0
AIN1
AIN2
AIN3
A0
A1
A2
V
SS
1
2
3
4
5
6
7
8
013aaa245
16 V
DD
15 AOUT
14 VREF
13 AGND
12 EXT
11 OSC
10 SCL
9
SDA
PCA9691T
Top view. For mechanical details, see
Figure 27.
Fig 4.
Pin configuration for SO16 (PCA9691T)
PCA9691_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 January 2010
3 of 31
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
HVQFN16
TSSOP16
SO16
(PCA9691BS) (PCA9691TS) (PCA9691T)
AIN0
AIN1
AIN2
AIN3
A0
A1
A2
V
SS
SDA
SCL
OSC
15
16
1
2
3
4
5
6
[1]
7
8
9
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
input
input
input
input
input
input
input
ground
input/output
input
input/output
analog input 0
analog input 1
analog input 2
analog input 3
address input 0
address input 1
address input 2
ground supply (analog and digital)
I
2
C-bus data input and output
I
2
C-bus clock input
oscillator signal selection:
input, if pin EXT is HIGH
output, if pin EXT is LOW
EXT
10
12
12
input
oscillator selection input:
HIGH: external oscillator
LOW: internal oscillator
AGND
VREF
AOUT
V
DD
11
12
13
14
[1]
Type
Description
13
14
15
16
13
14
15
16
ground
input
output
supply
DAC analog ground
DAC reference voltage input
analog output
supply voltage
The die paddle (exposed pad) is connected to V
SS
and should be electrically isolated.
7. Functional description
7.1 Addressing
Each PCA9691 device in an I
2
C-bus system is activated by sending a valid address to the
device. The address consists of seven programmable bits and one read/write bit. The
address must be set according to
Table 4.
The three input pins (A2, A1, and A0) are used
to encode the seven address bits (A[6:0]), where each of the pins can be connected to
V
DD
, V
SS
, SCL, or SDA. The address is always sent as the first byte after the start
condition in the I
2
C-bus protocol. The last bit of the address byte is the read/write bit which
sets the direction of the following data transfer (see
Figure 5, Figure 18,
and
Figure 19).
msb
A6
A5
A4
A3
A2
A1
A0
lsb
R/W
001aag465
Fig 5.
Address byte
PCA9691_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 January 2010
4 of 31
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
7.1.1 Address map
Table 4.
Pin
A2
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
SDA
SDA
SDA
SDA
V
SS
V
DD
SDA
SDA
SDA
SDA
SDA
SCL
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
SCL
SCL
SCL
SCL
V
SS
V
DD
SCL
SCL
SCL
SCL
PCA9691_2
PCA9691 address map
Bit
A1
V
SS
V
DD
V
SS
V
DD
SDA
SDA
SDA
SDA
V
SS
V
SS
V
DD
V
DD
SDA
SDA
V
SS
V
DD
SDA
SDA
SDA
SCL
V
SS
V
DD
V
SS
V
DD
SCL
SCL
SCL
SCL
V
SS
V
SS
V
DD
V
DD
SCL
SCL
V
SS
V
DD
SCL
SCL
A0
SDA
SDA
SDA
SDA
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
SDA
SDA
SDA
SDA
V
SS
V
DD
SDA
SCL
SCL
SCL
SCL
SCL
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
SCL
SCL
SCL
SCL
V
SS
V
DD
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Address Number
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 January 2010
5 of 31
