Datasheet
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs,
PCIe Gen 1 compliant
ICS9LPRS502
Key Specifications:
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 100ppm frequency accuracy on CPU & SRC
clocks
Output Features:
•
•
•
•
•
•
•
•
2 - CPU differential low power push-pull pairs
7 - SRC differential low power push-pull pairs
1 - CPU/SRC selectable differential low power push-pull
pair
1 - SRC/DOT selectable differential low power push-pull
pair
5 - PCI, 33MHz
1 - PCI_F, 33MHz free running
1 - USB, 48MHz
1 - REF, 14.318MHz
Features/Benefits:
•
•
•
•
•
Does not require external pass transistor for voltage
regulator
Integrated series resistors on differential outputs,
Z
o
=50W
Supports spread spectrum modulation, default is 0.5%
down spread
Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0
0
0
0
1
1
1
1
2
Pin Configuration
U
SB
MHz
DOT
MHz
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
56-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
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56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
ICS 9LPRS502
FS
L
B
B0b6
0
0
1
1
0
0
1
1
1
FS
L
A
B0b5
0
1
0
1
0
1
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
100.00
33.33
14.318
48.00
96.00
Reserved
PCICLK0/CR#_A
VDDPCI
PCICLK1/CR#_B
PCICLK2/LTE
PCICLK3
PCICLK4/SRC5_EN
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96I/O
DOTT_96/SRCCLKT0
DOTC_96/SRCCLKC0
GND
VDD
SRCCLKT1/SE1
SRCCLKC1/SE2
GND
VDDPLL3I/O
SRCCLKT2/SATACLKT
SRCCLKC2/SATACLKC
GNDSRC
SRCCLKT3/CR#_C
SRCCLKC3/CR#_D
VDDSRCI/O
SRCCLKT4
SRCCLKC4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SCLK
SDATA
FSLC/TEST_SEL/REF0
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPUI/O
NC
CPUCLKT2_ITP/SRCCLKT8
CPUCLKC2_ITP/SRCCLKC8
VDDSRCI/O
SRCCLKT7/CR#_F
SRCCLKC7/CR#_E
GNDSRC
SRCCLKT6
SRCCLKC6
VDDSRC
PCI_STOP#/SRCCLKT5
CPU_STOP#/SRCCLKC5
1125E—02/26/09
1
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI
output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI
output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-
up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output.
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the
logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is
enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state
of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an
ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground for PCI clocks.
Power supply for USB clock, nominal 3.3V.
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
Power supply for DOT96 output. 1.05 to 3.3V +/-5%.
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin
function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this
pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin for the DOT96 clocks.
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
1
PCI0/CR#_A
I/O
2
VDDPCI
PWR
3
PCI1/CR#_B
I/O
4
PCI2/TME
I/O
5
PCI3
OUT
6
PCI4/SRC5_EN
I/O
7
PCI_F5/ITP_EN
I/O
8
9
10
11
12
13
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
DOTT_96/SRCT0
PWR
PWR
I/O
PWR
PWR
OUT
14
15
16
DOTC_96/SRCC0
GND
VDD
OUT
PWR
PWR
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56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
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ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description (continued)
PIN #
17
18
19
20
21
22
23
PIN NAME
SRCT1/SE1
SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
PWR
DESCRIPTION
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100
MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default
is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
Power supply for PLL3 output. 1.05 to 3.3V +/-5%.
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin,
the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3
output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or
SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin,
the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3
output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
Power supply for SRC clocks. 1.05 to 3.3V +/-5%.
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
24
SRCT3/CR#_C
I/O
25
SRCC3/CR#_D
I/O
26
27
28
VDDSRC_IO
SRCT4
SRCC4
PWR
I/O
I/O
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56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
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ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
Stops all CPU Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap
on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as
follows:
0= CPU_STOP#
1 = SRC5
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap
on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as
follows:
0= PCI_STOP#
1 = SRC5#
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must
first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled
(high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of
SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8
via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be
disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z),
the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus
configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup.
The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is
as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
Supply for CPU outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during
iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
29
CPU_STOP#/SRCC5
I/O
30
PCI_STOP#/SRCT5
I/O
31
32
33
34
VDDSRC
SRCC6
SRCT6
GNDSRC
PWR
OUT
OUT
PWR
35
SRCC7/CR#_E
I/O
36
SRCT7/CR#_F
I/O
37
VDDSRC_IO
PWR
38
CPUC2_ITP/SRCC8
OUT
39
CPUT2_ITP/SRCT8
OUT
40
41
42
43
44
45
46
47
NC
VDDCPU_IO
CPUC1_F
CPUT1_F
GNDCPU
CPUC0
CPUT0
VDDCPU
N/A
PWR
OUT
OUT
PWR
OUT
OUT
PWR
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56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
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ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description (Continued)
PIN #
48
49
50
51
52
53
54
55
56
PIN NAME
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
TYPE
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
DESCRIPTION
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS
and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider
mode while in test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched
input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Fully Integrated Regulator Connection for Desktop/Mobile Applications
ICS9LPR502
ICS9LPRS502
VDDCPU_IO, Pin 41
1.05V to 3.3V
(+/-5%)
CPU_IO Decoupling
Network
NC
PIN 40
96_IO Decoupling
Network
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
VDDSRC_IO Pin 37, 26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
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56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
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