A25L80P
8 Mbit, Low Voltage, Serial Flash Memory
With 50 MHz SPI Bus Interface
Preliminary
Document Title
8 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface
Revision History
Rev. No.
0.0
History
Initial issue
Issue Date
May 30, 2005
Remark
PRELIMINARY
(May, 2005, Version 0.0)
AMIC Technology Corp.
A25L80P
8 Mbit, Low Voltage, Serial Flash Memory
With 50 MHz SPI Bus Interface
GENERAL DESCRIPTION
The A25L80P is an 8 Mbit (1M x 8) Serial Flash Memory, with
advanced write protection mechanisms, accessed by a high
speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 16 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole memory
can be viewed as consisting of 4096 pages, or 1,048,576
bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Preliminary
FEATURES
8 Mbit of Flash Memory
Flexible Sector Architecture (4/4/8/16/32)KB/64x15 KB
Bulk Erase (8 Mbit) in 10s (typical)
Sector Erase (512 Kbit) in 1s (typical)
Page Program (up to 256 Bytes) in 3ms (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
50MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Electronic Signature
- JEDEC Standard (13h)
Pin Configurations
SO8 Connections
SO16 Connections
A25L80P
A25L80P
S
Q
W
V
SS
1
2
3
4
8 V
CC
7 HOLD
6 C
5 D
HOLD
V
CC
DU
DU
DU
DU
S
Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
D
DU
DU
DU
DU
V
SS
W
Note:
DU = Do not Use
PRELIMINARY
(May 2005, Version 0.0)
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AMIC Technology Corp.
A25L80P
Block Diagram
HOLD
W
S
C
D
Q
I/C Shift Register
Control Logic
High Voltage
Generator
Address register
and Counter
256 Byte
Data Buffer
Status
Register
FFFFFh
Y Decoder
Size of the
read-only
memory area
000FFh
00000h
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
C
D
Q
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
Description
Logic Symbol
V
CC
D
C
S
W
HOLD
A25L80P
Q
S
W
HOLD
Vcc
Vss
V
SS
PRELIMINARY
(May 2005, Version 0.0)
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AMIC Technology Corp.
A25L80P
SIGNAL DESCRIPTION
Serial Data Output (Q).
This output signal is used to transfer
data serially out of the device. Data is shifted out on the falling
edge of Serial Clock (C).
Serial Data Input (D).
This input signal is used to transfer data
serially into the device. It receives instructions, addresses, and
the data to be programmed. Values are latched on the rising
edge of Serial Clock (C).
Serial Clock (C).
This input signal provides the timing of the
serial interface. Instructions, addresses, or data present at
Serial Data Input (D) are latched on the rising edge of Serial
Clock (C). Data on Serial Data Output (Q) changes after the
falling edge of Serial Clock (C).
Chip Select (
S
).
When this input signal is High, the device is
deselected and Serial Data Output (Q) is at high impedance.
Unless an internal Program, Erase or Write Status Register
cycle is in progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving Chip Select
(
S
) Low enables the device, placing it in the active power
mode.
After Power-up, a falling edge on Chip Select (
S
) is required
prior to the start of any instruction.
Hold (
HOLD
).
The Hold (
HOLD
) signal is used to pause any
serial communications with the device without deselecting the
device.
During the Hold condition, the Serial Data Output (Q) is high
impedance, and Serial Data Input (D) and Serial Clock (C) are
Don’t Care. To start the Hold condition, the device must be
selected, with Chip Select (
S
) driven Low.
Write Protect (
W
).
The main purpose of this input signal is to
freeze the size of the area of memory that is protected against
program or erase instructions (as specified by the values in the
BP2, BP1 and BP0 bits of the Status Register).
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge
of Serial Clock (C), and output data is available from the falling
edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
PRELIMINARY
(May 2005, Version 0.0)
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AMIC Technology Corp.
A25L80P
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SDO
SDI
SCK
C Q D
C Q D
C Q D
SPI Memory
Device
CS3
CS2
CS1
S
W HOLD
SPI Memory
Device
SPI Memory
Device
S
W HOLD
S
W HOLD
Note: The Write Protect (
W
) and Hold (
HOLD
) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL
0
1
CPHA
0
1
C
C
D
Q
MSB
MSB
PRELIMINARY
(May 2005, Version 0.0)
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AMIC Technology Corp.
