ABX2038/39
PECL and LVDS Low Phase Noise XO (for 65-130MHz Output)
FEATURES
•
•
•
•
•
•
65MHz to 130MHz Crystal input.
Output range: 32.5MHz – 130MHz (no PLL).
Low Injection Power for crystal, 50uW.
PECL (ABX2038) or LVDS output (ABX2039).
Supports 2.5V or 3.3V-Power Supply.
Available in 16-Pin TSSOP.
PIN CONFIGURATION
VDD
XIN
XOUT
N/C
S2
1
2
16
15
N/C
N/C
GND
CLKC
VDD
CLKT
N/C
N/C
ABX203x
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTION
The ABX2038/39 is a family of XO IC’s specifically
designed to work with high frequency fundamental or
3
rd
OT crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs. They achieve
very low current into the crystal resulting in better
overall stability. Their very low jitter makes them
ideal for the most demanding timing requirements.
OE
N/C
GND
BLOCK DIAGRAM
OUTPUT ENABLE LOGICAL LEVELS
OE
Q
XIN
XOUT
Oscillator
Amplifier
Part #
ABX2038
Q
ABX2039
S2
OE
0
(Default)
1
0
1
(Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for ABX2038
Logical states defined by CMOS levels for ABX2039
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
03/21/05 Page 1
ABX2038/39
PECL and LVDS Low Phase Noise XO (for 65-130MHz Output)
PIN DESCRIPTIONS
Name
XIN
XOUT
S2
OE
GND
CLKT
CLKC
N/C
VDD
Number
2
3
5
6
8, 14
11
13
4,7,9,10,15,16
1, 12
Type
I
I
I
I
P
O
O
-
P
Description
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
When pulled low the output is equal to the input divided by 2. Internal
pull up.
Output enable. See Output Enable Logic table on page 1.
Ground.
True output PECL (ABX2038) or LVDS (ABX2039).
Complementary output PECL (ABX2038) or LVDS (ABX2039).
Not connected.
Power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Oscillation Frequency
Crystal Load
Inter-electrode capacitance
SYMBOL
OF
CL
C
0
CONDITIONS
Fund
MIN.
65
TYP.
8.5
2.6
MAX.
130
UNITS
MHz
pF
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
03/21/05 Page 2
ABX2038/39
PECL and LVDS Low Phase Noise XO (for 65-130MHz Output)
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
MIN.
TYP.
MAX.
100/80
UNITS
mA
V
%
mA
2.97
45
45
50
50
±50
3.63
55
55
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Integrated jitter RMS
CONDITIONS
77.76MHz
77.76MHz
Integrated 12kHz to 20MHz at 77.76MHz
MIN.
TYP.
2.5
18.5
0.5
MAX.
UNITS
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
77.76MHz
@10Hz
-75
@100Hz
-95
@1kHz
-125
@10kHz
-145
@100kHz
-155
UNITS
dBc/Hz
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
03/21/05 Page 3
ABX2038/39
PECL and LVDS Low Phase Noise XO (for 65-130MHz Output)
6. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
7. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
03/21/05 Page 4
ABX2038/39
PECL and LVDS Low Phase Noise XO (for 65-130MHz Output)
8. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
MAX.
V
DD
– 1.620
UNITS
V
V
9. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
03/21/05 Page 5
DSP 与 ARM 处理器
