= +5 V; applies to each ADC, unless otherwise noted.)
Temp
Test
Level
Mil
Subgroup
Min
AD10242BZ/TZ
Typ
12
Guaranteed
±
0.05
±
1.0
±
0.1
±
0.5
±
0.8
±
0.1
Max
Unit
Bits
–0.5
–2.0
–1.0
–1.5
+0.5
+2.0
+1.0
+1.5
% FS
% FS
%
% FS
% FS
%
Full
Full
Full
Full
Full
Full
25°C
Full
I
I
I
IV
IV
IV
IV
V
12
12
12
12
99
198
396
0
±
0.5
±
1.0
±
2
100
200
400
4.0
60
TTL/CMOS
101
202
404
7.0
V
V
V
Ω
Ω
Ω
pF
MHz
Full
Full
Full
Full
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
I
I
I
I
V
VI
V
V
V
V
IV
IV
IV
V
I
II
I
II
I
II
V
I
II
I
II
I
II
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
12
4, 5, 6
12
2.0
0
–400
625
–300
5.0
0.8
800
7.0
V
V
µA
µA
pF
MSPS
MSPS
ns
ns
ps rms
ns
ns
ns
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
40
50
5
1.0
±
2.0
1
10
10
12
68
66
66
65
65
63
62
67
65
64
64
63
61
60
12
12
12
12
10
41
14
4
5, 6
4
5, 6
4
5, 6
63
62
63
62
60
59
4
5, 6
4
5, 6
4
5, 6
62
61
60
60
58
58
–2–
REV. D
AD10242
Parameter
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 1.2 MHz
@ 4.85 MHz
@ 9.9 MHz
@ 19.5 MHz
TWO-TONE IMD REJECTION
10
F1, F2 @ –7 dBFS
CHANNEL-TO-CHANNEL ISOLATION
11
TRANSIENT RESPONSE
LINEARITY
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
(
Encode
= 20 MHz)
OVERVOLTAGE RECOVERY TIME
12
V
IN
= 2.0
×
FS
V
IN
= 4.0
×
FS
DIGITAL OUTPUTS
Logic Compatibility
Logic “1” Voltage
13
Logic “0” Voltage
14
Output Coding
POWER SUPPLY
AV
CC
Supply Voltage
I (AV
CC
) Current
AV
EE
Supply Voltage
I (AV
EE
) Current
DV
CC
Supply Voltage
I (DV
CC
) Current
I
CC
(Total) Supply Current
Power Dissipation (Total)
Temp
25°C
25°C
Full
25°C
Full
25°C
Full
Full
25°C
25°C
25°C
Full
25°C
Test
Level
I
I
II
I
II
I
II
II
IV
V
IV
IV
V
12
12
Mil
Subgroup
Min
AD10242BZ/TZ
Typ
Max
81
80
79
70
69
67
66
76
80
10
0.3
0.5
0.3
1.0
1.25
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dB
ns
LSB
LSB
4
5, 6
4
5, 6
4
5, 6
4, 5, 6
12
70
70
63
63
60
60
70
75
Full
Full
V
IV
12
0.5
50
100
LSB
LSB
ns
Full
IV
12
75
200
ns
Full
Full
I
I
1, 2, 3
1, 2, 3
3.5
CMOS
4.2
0.45
0.65
Twos Complement
5.0
260
–5.0
55
5.0
25
350
1.75
V
V
Full
Full
Full
Full
Full
Full
Full
Full
VI
V
VI
V
VI
V
I
I
1, 2, 3
1, 2, 3
400
2.0
V
mA
V
mA
V
mA
mA
W
Power Supply Rejection Ratio (PSRR)
Pass-Band Ripple to 10 MHz
Full
Full
I
IV
7, 8
12
0.01
0.02
0.2
% FSR/% V
S
dB
NOTES
1
Gain tests are performed on A
IN
3 over specified input voltage range.
2
Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
ENCODE driven by single-ended source;
ENCODE
bypassed to ground through 0.01
µF
capacitor.
5
ENCODE may also be driven differentially in conjunction with
ENCODE;
see Encoding the AD10242 section for details.
6
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
±
5%.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9
Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz
±
100 kHz, 50 kHz
≤
f1 – f2
≤
300 kHz.
11
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A
IN
1).
12
Input driven to 2× and 4× A
IN
1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed.
13
Outputs are sourcing 10
µA.
14
Outputs are sinking 10
µA.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. D
–3–
AD10242
ABSOLUTE MAXIMUM RATINGS
1
Parameter
ELECTRICAL
V
CC
Voltage
V
EE
Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
ENCODE,
ENCODE
Differential Voltage
Digital Output Current
ENVIRONMENTAL
2
Operating Temperature (Case)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
Min
0
–7
V
EE
–10
0
–40
–55
Max
7
0
V
CC
+10
V
CC
4
+40
+125
175
300
+150
Unit
V
V
V
mA
V
V
mA
°C
°C
°C
°C
Table I. Output Coding
MSB
LSB
Base 10
2047
+1
0
–1, 4095
–2047, 2048
Input
+FS
0.0 V
–FS
0111111111111
0000000000001
0000000000000
1111111111111
1000000000000
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% Production Tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C; sample
tested at temperature extremes.
–65
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedances for
ES-68-1
package:
θ
JC
= 11°C/W;
θ
JA
= 30°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
