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AD5204BCPZ10-REEL

Digital Potentiometer 10kOhm 256POS Volatile Linear 32-Pin LFCSP EP T/R

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器件参数
参数名称
属性值
欧盟限制某些有害物质的使用
Compliant
ECCN (US)
EAR99
Part Status
Active
HTS
8542.39.00.01
Taper Type
Linear
Number of Pot per Package
4
位置数量
Number of Positions
256
Memory Type
Volatile
Resistance Value (kohm)
10
Minimum Single Supply Voltage (V)
2.7
Typical Single Supply Voltage (V)
3|5
Maximum Single Supply Voltage (V)
5.5
Maximum Dual Supply Voltage (V)
±2.7
Typical Dual Supply Voltage (V)
±2.5
Minimum Dual Supply Voltage (V)
±2.3
Maximum Supply Current (mA)
0.012(Typ)
Power Supply Type
Single|Dual
Minimum Operating Temperature (°C)
-40
Maximum Operating Temperature (°C)
85
Supplier Temperature Grade
Extended Industrial
系列
Packaging
Tape and Reel
Pin Count
32
Standard Package Name
CSP
Supplier Package
LFCSP EP
Mounting
Surface Mount
Package Height
0.83
Package Length
5
Package Width
5
PCB changed
32
Lead Shape
No Lead
参考设计
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Data Sheet
FEATURES
256 positions
Multiple independently programmable channels
AD5204—4-channel
AD5206—6-channel
Potentiometer replacement
Terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ
3-wire SPI-compatible serial data input
+2.7 V to +5.5 V single-supply operation; ±2.7 V dual-supply
operation
Power-on midscale preset
CS
CLK
4-/6-Channel
Digital Potentiometers
AD5204/AD5206
FUNCTIONAL BLOCK DIAGRAMS
AD5204
EN
A2
A1
A0
D7
ADDR
DEC
D0
D7
RDAC
LATCH
1
R
V
DD
A1
W1
B1
SDO
DO
SER
REG
D7
SDI
DI
D0
8
POWER-ON
PRESET
D0
RDAC
LATCH
4
R
A4
W4
B4
SHDN
V
SS
06884-001
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Line impedance matching
GND
PR
Figure 1.
CS
CLK
GENERAL DESCRIPTION
The
AD5204/AD5206
provide 4-/6-channel, 256-position
digitally controlled variable resistor (VR) devices. These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the
AD5204/ AD5206
contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a
digital code loaded into the SPI-compatible serial-input
register. The resistance between the wiper and either endpoint
of the fixed resistor varies linearly with respect to the digital code
transferred into the VR latch. The variable resistor offers a
completely programmable value of resistance between the
A terminal and the wiper or the B terminal and the wiper. The
fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ, or 100 kΩ has
a nominal temperature coefficient of 700 ppm/°C.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eleven data bits make up
the data-word clocked into the serial input register. The first
three bits are decoded to determine which VR latch is loaded
with the last eight bits of the data-word when the CS strobe is
returned to logic high. A serial data output pin at the opposite
end of the serial register (AD5204 only) allows simple daisy
chaining in multiple VR applications without requiring
additional external decoding logic.
AD5206
EN
A2
A1
A0
D7
ADDR
DEC
D0
D7
RDAC
LATCH
1
V
DD
A1
W1
B1
R
SER
REG
D7
SDI
A6
RDAC
LATCH
6
W6
B6
DI
D0
8
D0
R
V
SS
06884-002
GND
POWER-ON
PRESET
Figure 2.
An optional reset (PR) pin forces all the
AD5204
wipers to the
midscale position by loading 0x80 into the VR latch.
The
AD5204/AD5206
are available in the 24-lead surface-
mount SOIC, TSSOP, and PDIP packages. The
AD5204
is also
available in a 32-lead, 5 mm × 5 mm LFCSP package. All parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C. For additional single-, dual-, and quad-
channel devices, see the
AD8400/AD8402/AD8403
data sheets.
Rev. E
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
AD5204/AD5206
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications ...................................................................................... 1
 
General Description ......................................................................... 1
 
Functional Block Diagrams............................................................. 1
 
Revision History ............................................................................... 2
 
Specifications .................................................................................... 3
 
Electrical Characteristics ............................................................. 3
 
Timing Diagrams.............................................................................. 5
 
Absolute Maximum Ratings ........................................................... 6
 
ESD Caution.................................................................................. 6
 
Pin Configurations and Function Descriptions ........................... 7
 
Data Sheet
Typical Performance Characteristics .......................................... 10
 
Operation ........................................................................................ 12
 
Programming the Variable Resistor ............................................ 13
 
Rheostat Operation .................................................................... 13
 
Programming the Potentiometer Divider .................................. 14
 
Voltage Output Operation ........................................................ 14
 
Digital Interfacing .......................................................................... 15
 
Test Circuits .................................................................................... 16
 
Outline Dimensions ....................................................................... 17
 
Ordering Guide .......................................................................... 18
 
REVISION HISTORY
9/2020—Rev. D to Rev. E
Changed CP-32-3 to CP-32-13.................................... Throughout
Changes to Figure 7.......................................................................... 8
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
6/2015—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
7/2010—Rev. B to Rev. C
Changes to Digital Input and Output Voltage to GND
Parameter, Table 2............................................................................ 6
Changes to Ordering Guide .......................................................... 18
5/2009—Rev. A to Rev. B
Changes to Table 1 ............................................................................3
Changes to Absolute Maximum Ratings .......................................6
Changes to Figure 7 ..........................................................................8
Changes to Table 4 ............................................................................8
11/2007—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Added 32-Lead LFCSP Package ....................................... Universal
Changed R
BA
to R
AB
............................................................ Universal
Changes to Absolute Maximum Ratings .......................................6
Changes to Operation Section ...................................................... 12
Updated Outline Dimensions ...................................................... 17
Changes to Ordering Guide .......................................................... 18
9/1999—Revision 0: Initial Version
Rev. E | Page 2 of 20
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= 5 V ± 10% or 3 V ± 10%, V
SS
= 0 V, V
A
= V
DD
, V
B
= 0 V, −40°C < T
A
< +85°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS RHEOSTAT MODE
2
Resistor Differential NL
3
Resistor Nonlinearity Error
3
Nominal Resistor Tolerance
4
Resistance Temperature Coefficient
Nominal Resistance Match
Symbol
R-DNL
R-INL
ΔR
AB
ΔR
AB
/ΔT
ΔR/R
AB
Test Conditions/Comments
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
, wiper = no connect
Channel 1 to Channel 2, Channel 3, and
Channel 4, or to Channel 5 and Channel 6;
V
AB
= V
DD
I
W
= 1 V/R, V
DD
= 5 V
Min
−1
−2
−30
AD5204/AD5206
Typ
1
±0.25
±0.5
700
0.25
Max
+1
+2
+30
1.5
Unit
LSB
LSB
%
ppm/°C
%
Wiper Resistance
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
2
Resolution
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
6
Capacitance
7
Ax, Bx
Capacitance
7
Wx
Shutdown Current
8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
7
POWER SUPPLIES
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
7, 10
Bandwidth −3 dB
R
W
50
100
Ω
N
DNL
INL
ΔV
W
/ΔT
V
WFSE
V
WZSE
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
A_SD
I
CM
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
range
V
DD
/V
SS
range
I
DD
I
SS
P
DISS
PSS
BW_10K
BW_50K
BW_100K
THD
W
t
S
e
N_WB
8
−1
−2
Code = 0x40
Code = 0x7F
Code = 0x00
−2
0
V
SS
f = 1 MHz, measured to GND, code = 0x40
f = 1 MHz, measured to GND, code = 0x40
V
A
= V
B
= V
W
= 0, V
DD
= +2.7 V, V
SS
= −2.5 V
V
DD
= 5 V/3 V
V
DD
= 5 V/3 V
R
PULL–UP
= 1 kΩ to 5 V
I
OL
= 1.6 mA, V
LOGIC
= 5 V
V
IN
= 0 V or 5 V
2.4/2.1
±0.25
±0.5
15
−1
1
+1
+2
0
2
V
DD
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
nA
V
V
V
V
μA
pF
V
V
μA
μA
mW
%/%
kHz
kHz
kHz
%
μs
nV/√Hz
45
60
0.01
1
5
0.8/0.6
4.9
0.4
±1
5
V
SS
= 0 V
V
IH
= 5 V or V
IL
= 0 V
V
SS
= −2.5 V, V
DD
= +2.7 V
V
IH
= 5 V or V
IL
= 0 V
ΔV
DD
= 5 V ± 10%
R
AB
= 10 kΩ
R
AB
= 50 kΩ
R
AB
= 100 kΩ
V
A
= 1.414 V rms, V
B
= 0 V dc, f = 1 kHz
V
A
= 5 V, V
B
= 0 V, ±1 LSB error band
R
WB
= 5 kΩ, f = 1 kHz, PR = 0
2.7
±2.3
12
12
0.0002
721
137
69
0.004
2/9/18
9
5.5
±2.7
60
60
0.3
0.005
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage
Rev. E | Page 3 of 20
AD5204/AD5206
Parameter
INTERFACE TIMING CHARACTERISTICS
7, 11, 12
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK-to-SDO Propagation Delay
13
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Fall Setup
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
2
Data Sheet
Symbol
t
CH
, t
CL
t
DS
t
DH
t
PD
t
CSS
t
CSW
t
RS
t
CSH0
t
CSH1
t
CS1
Test Conditions/Comments
Clock level high or low
Min
20
5
5
1
15
40
90
0
0
10
Typ
1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 2 kΩ , C
L
< 20 pF
150
Typicals represent average readings at 25°C and V
DD
= 5 V.
Applies to all VRs.
3
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.
I
W
= V
DD
/R for both V
DD
= 3 V and V
DD
= 5 V.
4
V
AB
= V
DD
, wiper (V
W
) = no connect.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.
6
Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.
7
Guaranteed by design and not subject to production test.
8
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= 5 V.
11
Applies to all parts.
12
See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V
DD
= 3 V and V
DD
= 5 V.
13
The propagation delay depends on the values of V
DD
, R
L
, and C
L
(see the Operation section).
Rev. E | Page 4 of 20
Data Sheet
TIMING DIAGRAMS
SDI
1
0
CLK
1
0
CS
1
0
V
OUT
06884-003
AD5204/AD5206
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
RDAC LATCH LOAD
V
DD
0V
Figure 3. Timing Diagram
SDI
(DATA IN)
1
0
1
0
Ax OR Dx
Ax OR Dx
t
DS
Ax OR Dx
Ax OR Dx
t
DH
SDO
(DATA OUT)
1
CLK
0
1
0
t
CH
t
CSH0
t
CSS
t
PD_MAX
t
CS1
t
CL
t
CSH1
t
CSW
t
S
CS
0V
±1 LSB ERROR BAND
Figure 4. Detailed Timing Diagram
1
PR
0
t
RS
0V
±1 LSB ERROR BAND
Figure 5.
AD5204
Preset Timing Diagram
Rev. E | Page 5 of 20
06884-005
V
OUT
V
DD
t
S
±1 LSB
06884-004
V
OUT
V
DD
±1 LSB
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参数对比
与AD5204BCPZ10-REEL相近的元器件有:AD5204BRUZ50-REEL7、AD5204BCPZ10-REEL7、AD5204BRZ50-REEL、AD5204BRZ10。描述及对比如下:
型号 AD5204BCPZ10-REEL AD5204BRUZ50-REEL7 AD5204BCPZ10-REEL7 AD5204BRZ50-REEL AD5204BRZ10
描述 Digital Potentiometer 10kOhm 256POS Volatile Linear 32-Pin LFCSP EP T/R Digital Potentiometer 50kOhm 256POS Volatile Linear 24-Pin TSSOP T/R Digital Potentiometer 10kOhm 256POS Volatile Linear 32-Pin LFCSP EP T/R Digital Potentiometer 50kOhm 256POS Volatile Linear 24-Pin SOIC W T/R Digital Potentiometer 10kOhm 256POS Volatile Linear 24-Pin SOIC W Tube
欧盟限制某些有害物质的使用 Compliant Compliant Compliant Compliant -
ECCN (US) EAR99 EAR99 EAR99 EAR99 -
Part Status Active Active Active Active -
HTS 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01 -
Taper Type Linear Linear Linear Linear -
Number of Pot per Package 4 4 4 4 -
位置数量
Number of Positions
256 256 256 256 -
Memory Type Volatile Volatile Volatile Volatile -
Minimum Single Supply Voltage (V) 2.7 2.7 2.7 2.7 -
Typical Single Supply Voltage (V) 3|5 3|5 3|5 3|5 -
Maximum Single Supply Voltage (V) 5.5 5.5 5.5 5.5 -
Maximum Dual Supply Voltage (V) ±2.7 ±2.7 ±2.7 ±2.7 -
Typical Dual Supply Voltage (V) ±2.5 ±2.5 ±2.5 ±2.5 -
Minimum Dual Supply Voltage (V) ±2.3 ±2.3 ±2.3 ±2.3 -
Maximum Supply Current (mA) 0.012(Typ) 0.012(Typ) 0.012(Typ) 0.012(Typ) -
Power Supply Type Single|Dual Single|Dual Single|Dual Single|Dual -
Minimum Operating Temperature (°C) -40 -40 -40 -40 -
Maximum Operating Temperature (°C) 85 85 85 85 -
Supplier Temperature Grade Extended Industrial Extended Industrial Extended Industrial Extended Industrial -
系列
Packaging
Tape and Reel Tape and Reel Tape and Reel Tape and Reel -
Pin Count 32 24 32 24 -
Standard Package Name CSP SOP CSP SOP -
Supplier Package LFCSP EP TSSOP LFCSP EP SOIC W -
Mounting Surface Mount Surface Mount Surface Mount Surface Mount -
Package Height 0.83 1.05(Max) 0.83 2.35(Max) -
Package Length 5 7.8 5 15.6(Max) -
Package Width 5 4.4 5 7.6(Max) -
PCB changed 32 24 32 24 -
Lead Shape No Lead Gull-wing No Lead Gull-wing -
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