The AD5260/AD5262 contain 1968 transistors. Die size: 89 mil × 105 mil (9345 sq mil).
Table 1.
Parameter
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Resistor Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
Channel Resistance Matching (AD5262 only)
Resistance Drift
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE
Resolution
Differential Nonlinearity
4
Integral Nonlinearity
4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
5
Ax and Bx Capacitance
6
Wx Capacitance
6
Common-Mode Leakage Current
Shutdown Current
7
DIGITAL INPUTS and OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current
8
Input Capacitance
6
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
9
Power Supply Sensitivity
Symbol
R-DNL
R-INL
ΔR
AB
ΔR
AB
/ΔT
R
W
ΔR
WB
/R
WB
ΔR
AB
Specifications apply to all VRs
N
DNL
INL
ΔV
W
/ΔT
W
FSE
V
WZSE
V
A, B, W
C
A,B
C
W
I
CM
I
SHDN
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
L
V
DD RANGE
V
DD/SS RANGE
I
L
I
DD
I
SS
P
DISS
PSS
8
−1
−1
Code = half scale
Code = full scale
Code = zero scale
−2
0
V
SS
f = 5 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
V
A
= V
B
= V
DD
/2
25
55
1
5
2.4
0.8
V
L
= 3 V, V
SS
= 0 V
V
L
= 3 V, V
SS
= 0 V
R
PULL-UP
= 2 kΩ to 5 V
I
OL
= 1.6 mA, V
LOGIC
= 5 V
V
IN
= 0 V or 5 V
2.1
0.6
4.9
0.4
±1
5
2.7
4.5
±4.5
5.5
16.5
±5.5
60
1
1
0.3
0.003
0.01
±1/4
±1/2
5
−1
1
+1
+1
+0
2
V
DD
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
μA
V
V
V
V
V
V
μA
pF
V
V
V
μA
μA
μA
mW
%/%
Conditions
Specifications apply to all VRs
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
Wiper = no connect
I
W
= 1 V/R
AB
Channel 1 and Channel 2 R
WB
,
D
X
= 0x80
Min
−1
−1
−30
Typ
1
±¼
±½
35
60
0.1
0.05
Max
+1
+1
30
150
Unit
LSB
LSB
%
ppm/°C
Ω
%
%
V
SS
= 0 V
V
L
= 5 V
V
IH
= 5 V or V
IL
= 0 V
V
SS
= −5 V
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= +5 V, V
SS
= –5 V
ΔV
DD
= +5 V, ±10%
Rev. A | Page 3 of 24
AD5260/AD5262
Parameter
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Crosstalk
11
Symbol
BW
THD
W
t
S
C
T
Conditions
R
AB
= 20 kΩ/50 kΩ/200 kΩ
V
A
= 1 V
RMS
, V
B
= 0 V, f = 1 kHz,
R
AB
= 20 kΩ
V
A
= +5 V, V
B
= −5 V, ±1 LSB
error band, R
AB
= 20 kΩ
V
A
= V
DD
, V
B
= 0 V, measure V
W
with adjacent RDAC making
full-scale code change (AD5262
only)
V
A1
= V
DD
, V
B1
= 0 V, measure V
W1
with V
W2
= 5 V p-p at f = 10 kHz,
R
AB
= 20 kΩ/200 kΩ (AD5262
only)
R
WB
= 20 kΩ, f = 1 kHz
Specifications apply to all parts
Clock level high or low
20
10
10
1
5
20
50
0
10
Min
Typ
1
310/130/30
0.014
5
1
Max
Unit
kHz
%
μs
nV-sec
Analog Crosstalk
C
TA
–64
dB
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS
6, 12
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
13
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
2
e
N_WB
f
CLK
t
CH
, t
CL
t
DS
t
DH
t
PD
t
CSS
t
CSW
t
RS
t
CSH
t
CS1
13
25
nV/√Hz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 1 kΩ, C
L
< 20 pF
160
Typical values represent average readings at 25°C and V
DD
= +5 V, V
SS
=
−5
V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V and
V
SS
= −5V.
3
V
AB
= V
DD
, wiper = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V, V
SS
= −5 V, V
L
= +5 V.
11
Measured at V
W
where an adjacent V
W
is making a full-scale voltage change.
12
See Figure 5 for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
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