AN-223: AD7575 Operation with an Offset Signal Ground
for Disk Drive Applications
Data Sheet
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AD7575: CMOS, 5µs 8-Bit Sampling ADC Data Sheet
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AD7575: Military Data Sheet
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MS-2210: Designing Power Supplies for High Speed ADC
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AD7575–SPECIFICATIONS
Parameter
ACCURACY
Resolution
Total Unadjusted Error
Relative Accuracy
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Full-Scale Error
+25°C
T
MIN
to T
MAX
Offset Error
2
+25°C
T
MIN
to T
MAX
ANALOG INPUT
Voltage Range
DC Input Impedance
Slew Rate, Tracking
SNR
3
REFERENCE INPUT
V
REF
(For Specified Performance)
I
REF
LOGIC INPUTS
CS, RD
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
I
IN
, Input Current
+25°C
T
MIN
to T
MAX
C
IN
, Input Capacitance
3
CLK
V
lNL
, Input Low Voltage
V
INH
, Input High Voltage
I
INL
, Input Low Current
I
INH
, Input High Current
LOGIC OUTPUTS
BUSY,
DB0 to DB7
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
DB0 to DB7
Floating State Leakage Current
Floating State Output Capacitance
3
CONVERSION TIME
4
With External Clock
With Internal Clock, T
A
= +25°C
POWER REQUIREMENTS
5
V
DD
I
DD
Power Dissipation
Power Supply Rejection
8
±
2
±
1
8
±
1
±
1
±
1/2
±
1/2
0 to 2 V
REF
10
0.386
45
1.23
500
(V
DD
= +5 V, V
REF
= +1.23 V, AGND = DGND = 0 V; f
CLK
= 4 MHz external;
all specifications T
MIN
to T
MAX
unless otherwise noted)
S Version
8
±
2
±
1
8
±
1
±
1
±
1/2
±
1/2
0 to 2 V
REF
10
0.386
45
1.23
500
T Version
8
±
1
±
1/2
8
±
1
±
1
±
1/2
±
1/2
0 to 2 V
REF
10
0.386
45
1.23
500
Units
Bits
LSB max
LSB max
Bits max
LSB max
LSB max
LSB max
LSB max
Volts
MΩ min
V/µs max
dB min
Volts
µA
max
Full-Scale TC Is Typically 5 ppm/°C
Conditions/Comments
J, A Versions
1
K, B Versions
8
±
1
±
1/2
8
±
1
±
1
±
1/2
±
1/2
0 to 2 V
REF
10
0.386
45
1.23
500
Offset TC Is Typically 5 ppm/°C
1 LSB = 2 V
REF
/256; See Figure 16
V
IN
= 2.46 V p-p @ 10 kHz; See Figure 11
±
5%
0.8
2.4
±
1
±
10
10
0.8
2.4
700
700
0.8
2.4
±
1
±
10
10
0.8
2.4
700
700
0.8
2.4
±
1
±
10
10
0.8
2.4
800
800
0.8
2.4
±
1
±
10
10
0.8
2.4
800
800
V max
V min
µA
max
µA
max
pF max
V max
V min
µA
max
µA
max
V
IN
= 0 or V
DD
V
IN
= 0 or V
DD
V
INL
= 0 V
V
INH
= V
DD
0.4
4.0
±
1
10
5
5
15
+5
6
15
±
1/4
0.4
4.0
±
1
10
5
5
15
+5
6
15
±
1/4
0.4
4.0
±
10
10
5
5
15
+5
7
15
±
1/4
0.4
4.0
±
10
10
5
5
15
+5
7
15
±
1/4
V max
V min
µA
max
pF max
µs
µs
min
µs
max
Volts
mA max
mW typ
LSB max
I
SINK
= 1.6 mA
I
SOURCE
= 40
µA
V
OUT
= 0 to V
DD
f
CLK
= 4 MHz
Using Recommended Clock
Components Shown in Figure 15
±
5% for Specified Performance
Typically 3 mA with V
DD
= +5 V
4.75 V
≤
V
DD
≤
5.25 V
NOTES
1
Temperature ranges are as follows:
J, K Versions; 0°C to +70°C
A, B Versions; –25°C to +85°C
S, T Versions; –55°C to +125°C
2
Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB.
3
Sample tested at +25°C to ensure compliance.
4
Accuracy may degrade at conversion times other than those specified.
5
Power supply current is measured when AD7575 is inactive i.e., when
CS
=
RD
=
BUSY
= logic HIGH.
Specifications subject to change without notice.
–2–
REV. B
AD7575
TIMING SPECIFICATIONS
1
(V
Parameter
t
1
t
2
t
32
t
4
t
5
t
62
t
73
t
8
Limit at +25 C
(All Versions)
0
100
100
100
0
80
10
80
0
0
100
100
100
0
80
10
80
0
DD
= +5 V, V
REF
= +1.23 V, AGND = DGND = 0 V)
Limit at T
MIN
, T
MAX
(S, T Versions)
0
120
120
120
0
100
10
100
0
Units
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns max
ns min
Conditions/Comments
CS
to
RD
Setup Time
RD
to
BUSY
Propagation Delay
Data Access Time after
RD
RD
Pulse Width
CS
to
RD
Hold Time
Data Access Time after
BUSY
Data Hold Time
BUSY
to
CS
Delay
Limit at T
MIN
, T
MAX
(J, K, A, B Versions)
NOTES
1
Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10% to 90% of +5 V)
and timed from a voltage level of 1.6 V.
2
t
3
and t
6
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
