Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
•
MS-2210: Designing Power Supplies for High Speed ADC
•
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
•
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
DOCUMENTATION
Application Notes
• AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
•
AN-283: Sigma-Delta ADCs and DACs
•
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
•
AN-388: Using Sigma-Delta Converters-Part 1
•
AN-389: Using Sigma-Delta Converters-Part 2
•
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
Data Sheet
•
AD7721: CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC Data
Sheet
DESIGN RESOURCES
•
AD7721 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD7721 EngineerZone Discussions.
TOOLS AND SIMULATIONS
•
Sigma-Delta ADC Tutorial
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD7721–SPECIFICATIONS
Parameter
SERIAL MODE ONLY
STATIC PERFORMANCE
Resolution
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Differential Nonlinearity
Integral Nonlinearity
DC CMRR
Offset Error
2
Unipolar Mode
Bipolar Mode
Full-Scale Error
2, 3
Unipolar Mode
Bipolar Mode
Unipolar Offset Drift
Bipolar Offset Drift
ANALOG INPUTS
Signal Input Span (VIN1–VIN2)
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
REFERENCE INPUTS
V
REFIN
REFIN Input Current
DYNAMIC SPECIFICATIONS
Signal to (Noise + Distortion)
Total Harmonic Distortion
Frequency Response
0 kHz–210 kHz
229.2 kHz
259.01 kHz to 14.74 MHz
CLOCK
CLK Duty Ratio
V
CLKH
, CLK High Voltage
V
CLKL
, CLK Low Voltage
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
I
DD
(Total from AV
DD
, DV
DD
)
Power Consumption
Power Consumption
A Version
16
12
±
8
±
16
70
±
3.66
±
3.66
±
4.88
±
4.88
0.05
0.04
1
(AV
DD
= +5 V
5%; DV
DD
= +5 V 5%; AGND = DGND = 0 V,
f
CLK
= 15 MHz, REFIN = +2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
S Version
Units
Test Conditions/Comments
16
12
±
8
±
16
70
±
3.66
±
3.66
±
4.88
±
4.88
0.05
0.04
Bits
Bits min
LSB typ
LSB max
dB min
mV max
mV max
mV max
mV max
mV/°C typ
mV/°C typ
Guaranteed 12 Bits Monotonic
16-Bit Operation
Bipolar Mode
Typically 0.61 mV
Typically 0.61 mV
Typically 0.61 mV
Typically 1.22 mV
±
V
REFIN
/2
0 to V
REFIN
AV
DD
0
1.6
2 f
CLK
20.8
2.4 to 2.6
200
74
–78
±
0.05
–3
–72
45 to 55
0.7
×
DV
DD
0.3
×
DV
DD
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
±
V
REFIN
/2
0 to V
REFIN
AV
DD
0
1.6
2 f
CLK
20.8
2.4 to 2.6
200
74
–78
±
0.05
–3
–72
45 to 55
0.7
×
DV
DD
0.3
×
DV
DD
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
Volts max
Volts max
Volts
Volts
pF typ
MHz
kΩ typ
V min/V max
µA
typ
dB min
dB max
dB max
dB min
dB min
% max
V min
V max
V min
V max
µA
max
pF max
V min
V max
V min/V max
V min/V max
mA max
mW max
µW
max
UNI
= V
IH
UNI
= V
IL
Guaranteed by Design
With 15 MHz on CLK Pin
Input Bandwidth 0 kHz to 210 kHz
Input Bandwidth 0 kHz to 229.2 kHz
For Specified Operation
CLK Uses CMOS Logic
|I
OUT
|
≤
200
µA
|I
OUT
|
≤
1.6 mA
Digital Inputs Equal to 0 V or DV
DD
Active Mode
Standby Mode
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2
Applies after calibration at temperature of interest.
3
Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Specifications subject to change without notice.
–2–
REV. A
SPECIFICATIONS
Parameter
1
(AV
DD
= +5 V
5%; DV
DD
= +5 V 5%; AGND = DGND = 0 V, f
CLK
= 10 MHz,
REFIN = +2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
A Version
S Version
Units
AD7721
Test Conditions/Comments
PARALLEL MODE ONLY
STATIC PERFORMANCE
Resolution
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Differential Nonlinearity
Integral Nonlinearity
DC CMRR
Offset Error
2
Unipolar Mode
Bipolar Mode
Full-Scale Error
2, 3
Unipolar Mode
Bipolar Mode
Unipolar Offset Drift
Bipolar Offset Drift
ANALOG INPUTS
Signal Input Span (VIN1–VIN2):
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
REFERENCE INPUTS
V
REFIN
REFIN Input Current
DYNAMIC SPECIFICATIONS
Signal to (Noise + Distortion)
Total Harmonic Distortion
Frequency Response
0 kHz–140 kHz
152.8 kHz
172.67 kHz to 9.827 MHz
CLOCK
CLK Duty Ratio
V
CLKH
, CLK High Voltage
V
CLKL
, CLK Low Voltage
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
I
DD
(Total from AV
DD
, DV
DD
)
Power Consumption
Power Consumption
12
12
±
1/2
±
1/2
70
±
3.66
±
3.66
±
4.88
±
4.88
0.04
0.035
12
12
±
1/2
±
1/2
70
±
3.66
±
3.66
±
4.88
±
4.88
0.04
0.035
Bits
Bits min
LSB typ
LSB typ
dB min
mV max
mV max
mV max
mV max
mV/°C typ
mV/°C typ
Guaranteed 12 Bits Monotonic
12-Bit Operation
Bipolar Mode
Typically 0.61 mV
Typically 0.61 mV
Typically 0.61 mV
Typically 1.22 mV
±
V
REFIN
/2
0 to V
REFIN
AV
DD
0
1.6
2 f
CLK
31.25
2.4 to 2.6
200
70
–78
±
0.05
–3
–72
45 to 55
0.7
×
DV
DD
0.3
×
DV
DD
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
±
V
REFIN
/2
0 to V
REFIN
AV
DD
0
1.6
2 f
CLK
31.25
2.4 to 2.6
200
70
–78
±
0.05
–3
–72
45 to 55
0.7
×
DV
DD
0.3
×
DV
DD
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
Volts max
Volts max
Volts
Volts
pF typ
MHz
kΩ typ
V min/V max
µA
typ
dB min
dB max
dB max
dB min
dB min
% max
V min
V max
V min
V max
µA
max
pF max
V min
V max
V min/V max
V min/V max
mA max
mW max
µW
max
UNI
= V
IH
UNI
= V
IL
Guaranteed by Design
With 10 MHz on CLK Pin
Input Bandwidth 0 kHz to 140 kHz
Input Bandwidth 0 kHz to 152.8 kHz
For Specified Operation
CLK Uses CMOS Logic
|I
OUT
|
≤
200
µA
|I
OUT
|
≤
1.6 mA
Digital Inputs Equal to 0 V or DV
DD
Active Mode
Standby Mode
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2
Applies after calibration at temperature of interest.
3
Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Specifications subject to change without notice.
REV. A
–3–
AD7721
TIMING CHARACTERISTICS
Parameter
Serial Interface
f
CLK3
t
CLK LO
t
CLK HI
t
1
t
2 4
t
3
t
4
t
5
t
6
t
7
t
8 5
t
9
Parallel Interface
f
CLK3
t
CLK LO
t
CLK HI
Read Operation
t
10
t
11
t
12
Write Operation
t
13
t
14
t
15
1, 2
(AV
DD
= +5 V
5%; DV
DD
= +5 V
unless otherwise noted)
Units
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns max
ns nom
ns nom
ns max
ns min
ns min
ns max
ns nom
kHz min
MHz max
ns min
ns min
ns nom
ns max
ns nom
ns min
ns min
ns min
5%; AGND = DGND = 0 V, REFIN = +2.5 V
Limit at T
MIN
, T
MAX
(A, S Versions)
100
15
0.45
×
t
CLK
0.45
×
t
CLK
t
CLK
t
CLK HI
– 10
20
t
CLK HI
t
CLK LO
25
0
0
20
32
×
t
CLK
100
10
0.45
×
t
CLK
0.45
×
t
CLK
2
×
t
CLK
30
32
×
t
CLK
35
20
0
Conditions/Comments
Master Clock Frequency
15 MHz for Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
DRDY
High Time
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
Period between Consecutive
DRDY
Rising Edges
Master Clock Frequency
10 MHz for Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
DRDY
High Time
Data Access Time after Falling Edge of
DRDY
Period between Consecutive
DRDY
Rising Edges
WR
Pulse Width
Data Valid to
WR
High Setup Time
Data Valid to
WR
High Hold Time
NOTES
The timing is measured with a load of 50 pF on SCLK and
DRDY.
SCLK can be operated with a load capacitance of 50 pF maximum.
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
All digital outputs are timed with the load circuit below and, except for t
2
, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
3
The AD7721 is production tested with f
CLK
at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.
4
t
2
is the time from
RFS
crossing 1.6 V to SCLK crossing 0.8 V.
5
t
8
and t
15
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
1.6mA
I
OL
TO
OUTPUT
PIN
+1.6V
C
L
50pF
I
OH
200 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
